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Chapter 2:
SelectIO Logic Resources
IDELAY_TYPE Attribute
The IDELAY_TYPE attribute sets the type of delay used.
When the IDELAY_TYPE attribute is set to FIXED, the tap-delay value is fixed at the
number of taps determined by the IDELAY_VALUE attribute setting. This value is preset
and cannot be changed after configuration.
When the IDELAY_TYPE attribute is set to VARIABLE, the variable tap delay is selected.
The tap delay can be incremented by setting CE = 1 and INC = 1, or decremented by CE = 1
and INC = 0. The increment/decrement operation is synchronous to C.
When the IDELAY_TYPE attribute is set to VAR_LOAD or VAR_LOAD_PIPE, the variable
tap delay can be changed and dynamically loaded. The tap delay can be incremented by
setting CE = 1 and INC = 1, or decremented by CE = 1 and INC = 0. The increment/
decrement operation is synchronous to C. The LD pin in this mode loads the value
presented on CNTVALUEIN in VAR_LOAD mode or the value previously written to the
pipeline register in VAR_LOAD_PIPE mode. This allows the tap value to be dynamically
set.
IDELAY_VALUE Attribute
The IDELAY_VALUE attribute specifies the initial number of tap delays. The possible
values are any integer from 0 to 31. The default value is zero. The value of the tap delay
reverts to IDELAY_VALUE when the tap delay is reset (by asserting the LD pin). In
VARIABLE mode this attribute determines the initial setting of the delay line. In
VAR_LOAD or VAR_LOAD_PIPE mode, this attribute is not used, and the initial value of
the delay line is therefore always zero.
HIGH_PERFORMANCE_MODE Attribute
When TRUE, this attribute reduces the output jitter. This reduction in jitter results in a
slight increase in power dissipation from the IDELAYE2 primitive.
SIGNAL_PATTERN Attribute
Clock and data signals have different electrical profiles and therefore accumulate different
amounts of jitter in the IDELAY chain. By setting the SIGNAL_PATTERN attribute, the
user enables timing analyzer to account for jitter appropriately when calculating timing. A
clock signal is periodic in nature and does not have long sequences of consecutive ones or
zeroes, while data is random in nature and can have long and short sequences of ones and
zeroes.
IDELAY Modes
When used as IDELAY, the data input comes from either IBUF or the FPGA logic and the
output goes to ILOGICE2/ISERDESE2 or ILOGICE3/ISERDESE2. There are four modes of
operation available:
•
•
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Fixed delay mode (IDELAY_TYPE = FIXED)
In the fixed delay mode, the delay value is preset at configuration to the tap number
determined by the attribute IDELAY_VALUE. Once configured, this value cannot be
changed. When used in this mode, the IDELAYCTRL primitive must be instantiated.
See
IDELAYCTRL Usage and Design Guidelines
Variable delay mode (IDELAY_TYPE = VARIABLE)
In the variable delay mode, the delay value can be changed after configuration by
manipulating the control signals CE and INC. When used in this mode, the
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7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
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