Idelayctrl Timing; Idelayctrl Locations - Xilinx SelectIO 7 Series User Manual

RDY - Ready
The ready (RDY) signal indicates when the IDELAY and ODELAY modules in the specific
region are calibrated. The RDY signal is deasserted if REFCLK is held High or Low for
more than one clock period. If RDY is deasserted Low, the IDELAYCTRL module must be
reset. The implementation tools allow RDY to be unconnected/ignored.
illustrates the timing relationship between RDY and RST.

IDELAYCTRL Timing

Table 2-9
Table 2-9: IDELAYCTRL Switching Characteristics
F
IDELAYCTRL_REF_PRECISION
T
As shown in
X-Ref Target - Figure 2-15

IDELAYCTRL Locations

IDELAYCTRL modules exist in every I/O column in every clock region. An IDELAYCTRL
module calibrates all the IDELAYE2 and ODELAYE2 modules within its clock region. See
the 7 Series FPGA Clocking User Guide for the definition of a clock region.
Figure 2-16
7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
shows the IDELAYCTRL switching characteristics.
Symbol
IDELAYCTRL_REF
IDELAYCTRLCO_RDY
Figure 2-15, the 7 series FPGA IDELAYCTRL RST is an edge-triggered signal.
REFCLK
RST
RDY
Figure 2-15: Timing Relationship Between RST and RDY
illustrates the relative locations of the IDELAYCTRL modules.
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Description
REFCLK frequency
REFCLK precision
Reset/Startup to Ready for IDELAYCTRL
T
IDELAYCTRLCO_RDY
IDELAYCTRL
Figure 2-15
ug471_c2_13_011811
125
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