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More information including instantiation techniques and available attributes for these and
all other design primitives is available in UG768: Xilinx 7 Series FPGA Libraries Guide for
HDL Designs.
IBUF and IBUFG
Signals used as inputs to 7 series devices must use an input buffer (IBUF). The generic
7 series FPGA IBUF primitive is shown in
X-Ref Target - Figure 1-15
The IBUF and IBUFG primitives are the same. IBUFGs are used when an input buffer is
used as a clock input. In the Xilinx software tools, an IBUFG is automatically placed at
clock input sites.
IBUF_IBUFDISABLE
The IBUF_IBUFDISABLE primitive shown in
port that can be used as an additional power saving feature for periods when the input is
not used.
X-Ref Target - Figure 1-16
The IBUF_IBUFDISABLE primitive can disable the input buffer and force the O output to
the fabric to a logic High when the USE_IBUFDISABLE attribute is set to TRUE and the
IBUFDISABLE signal is asserted High. If USE_IBUFDISABLE is set to FALSE, this input is
ignored and should be tied to ground. This feature can be used to reduce power at times
when the I/O is idle. Input buffers that use the V
benefit the most from the IBUFDISABLE being set to TRUE because they tend to have
higher static power consumption than the non-VREF standards such as LVCMOS and
LVTTL.
7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
I (Input)
From device pad
Figure 1-15: Input Buffer Primitives (IBUF/IBUFG)
IBUFDISABLE
Figure 1-16: Input Buffer With Input Buffer Disable (IBUF_IBUFDISABLE)
www.xilinx.com
7 Series FPGA SelectIO Primitives
Figure
1-15.
IBUF/IBUFG
ug471_c1_17_011811
Figure 1-16
is an input buffer with a disable
IBUF_IBUFDISABLE
I
power rail (such as SSTL and HSTL)
REF
O (Output)
into FPGA
O
UG471_c1_63_041412
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