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Xilinx LogiCore PLB PCI Full Bridge Specification
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Xilinx LogiCore PLB PCI Full Bridge Specification

Xilinx LogiCore PLB PCI Full Bridge Specification

Xilinx inc. plb pci full bridge product specification
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DS508 March 21, 2006
Introduction
The PLB PCI Full Bridge design provides full bridge
functionality between the Xilinx 64-bit PLB and a 32-bit
Revision 2.2 compliant Peripheral Component
Interconnect (PCI) bus. The bridge is referred to as the
PLB PCI Bridge in this document.
The Xilinx PLB is a 64-bit bus subset of the IBM PLB
described in the 64-Bit Processor Local Bus Architecture
Specification v3.5. Details on the Xilinx PLB and the PLB
IPIF are found in the Processor IP Reference Guide. This
guide is accessed via EDK help or the Xilinx website at:
http://www.xilinx.com/ise/embedded/proc_ip_ref_
guide.pdf.
The LogiCORE PCI v3.0 core provides an interface with
the PCI bus. Details of the LogiCORE PCI 32 v3.0 core
operation is found in the
v3.0 Product Specification
and the
Design Guide
v3.0.
Host bridge functionality (often called North bridge
functionality) is an optional functionality.
Configuration Read and Write PCI commands can be
performed from the PLB-side of the bridge. The PLB
PCI Bridge supports a 32-bit/33 MHz PCI bus only.
Exceptions to the support of PCI commands supported
by the v3.0 core are outlined in the
The PLB PCI Bridge design has parameters that allow
customers to configure the bridge to suit their
application. The parameterizable features of the design
are discussed in the
Bus Interface Parameters
© 2005 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and
registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application,
or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implemen-
tation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this imple-
mentation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.
DS508 March 21, 2006
Product Specification
Xilinx LogiCORE PCI Interface
Xilinx The Real-PCI
Features
section.
section.
0
PLB PCI Full Bridge (v1.00a)
0
0
LogiCORE™ Facts
Supported Device
Family
Version of Core
Virtex-IIP
I/O (PCI)
I/O (PLB-related)
LUTs
FFs
Block RAMs
Provided with Core
Documentation
Design File Formats
Constraints File
Verification
Instantiation Template
Reference Designs
Design Tool Requirements
Xilinx Implementation
Tools
Verification
Simulation
Synthesis
Support provided by Xilinx, Inc.
www.xilinx.com
Product Specification
Core Specifics
Virtex™-II Pro, Virtex-4
plb_pci
v1.00a
Resources Used
Min
49
397
3350
3870
2570
2970
8
Product Specification
VHDL
example UCF-file
N/A
N/A
None
8.1.1i or later
N/A
ModelSim SE/EE 5.8d or later
XST
Support
Max
50
433
8
1

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Summary of Contents for Xilinx LogiCore PLB PCI Full Bridge

  • Page 1 NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implemen- tation.
  • Page 2 • Includes a slave IP module for remote PLB master transactions, which follows the protocol for interfacing with the slave IPIF module utilizing Xilinx IPIC protocol. The PLB PCI Bridge translates the PLB master request to PCI initiator transactions. The SRAM-like interface is utilized at the IPIC interface for data transfers.
  • Page 3 • Input signal to provide the means to asynchronous asset INTR_A from a user supplied register (i.e., a PLB GPIO). The signal is Bus2PCI_INTR is an active high signal • PCI Monitor output port to monitor PCI bus activity DS508 March 21, 2006 Product Specification PLB PCI Full Bridge (v1.00a) www.xilinx.com...

  • Page 4: System Reset

    LogiCore Version 3.0 32-bit PCI Core Requirements The PLB PCI bridge uses the 32-bit Xilinx LogiCore Version 3 IP core. Before the bridge can perform transactions on the PCI bus, the v3.0 core must be configured via configuration transactions from either the PCI-side or if configuration functionality is included in the bridge configuration, from the PLB-side.
  • Page 5 These documents detail the v3.0 core operation, including configuration cycles, and are available from Xilinx. As required by the LogiCORE v3.0 core, GNT_N must be asserted for two clock cycles to initiate a PCI transaction by the PLB PCI Bridge.
  • Page 6 LogiCORE PCIBAR_0 C_PCIBAR_NUM = 2 PBAR_20 PBAR_21 PBAR_22 is for an PLB PCI Bridge configuration with FIFOs only. In this example, it www.xilinx.com IPIFBAR_5 IPIFBAR_4 IPIF to v3.0 LogiCORE Bridge Addr to PLB Note 2 (high-order bit sub)
  • Page 7 BAR 1 is set to 0x12000000 by host C_PCIBAR_LEN_1=25 C_PCIBAR2IPIFBAR_1=0xFEXXXXXX (Bits 7-31 are don’t cares) Accessing the PLB PCI Bridge PCIBAR_0 with address 0xABCDEFF4 on the PCI bus yields 0x123457F4 on the PLB bus. DS508 March 21, 2006 Product Specification PLB PCI Full Bridge (v1.00a) www.xilinx.com...
  • Page 8 C_PLB_AWIDTH 0 = I/O space C_IPIF_SPACE TYPE_1 1 = Memory space C_IPIFBAR_2 Valid PLB address C_IPIFBAR_ Valid PLB address HIGHADDR_2 C_IPIFBAR2 Vector of length PCIBAR_2 C_PLB_AWIDTH www.xilinx.com Default VHDL Value Type integer std_logic_ 0xFFFFFFFF vector std_logic_ 0x00000000 vector std_logic_ 0xFFFFFFFF...
  • Page 9 C_PCIBAR_ valid values. BAR label 0 is the required bar for all values 1-3 and the index increments from 0 as BARs are added www.xilinx.com PLB PCI Full Bridge (v1.00a) Default VHDL Value Type integer std_logic_...
  • Page 10 0 = not included REQ_N_BUF 1 = included 5 to the lesser of 24 or the PCI2IPIF FIFO C_TRIG_PCI_ DEPTH-3. PCI2IPIF READ_OCC_ FIFO DEPTH given by LEVEL 2^C_PCI2IPIF_FIFO_ ABUS_WIDTH www.xilinx.com Default VHDL Value Type std_logic_ 0x00000000 vector integer std_logic_ 0x00000000 vector...
  • Page 11 ADDR (1), (2) C_HIGHADDR Valid PLB address C_INCLUDE_ 1 = include BAROFFSET_ 0 = exclude C_INCLUDE_D 1 = include EVNUM_REG 0 = exclude www.xilinx.com PLB PCI Full Bridge (v1.00a) Default VHDL Value Type integer integer integer integer integer integer std_logic_...
  • Page 12 16-bit vector C_CLASS_ 24-bit vector CODE C_REV_ID 8-bit vector C_SUB 16-bit vector SYSTEM_ID C_SUBSYSTE M_VENDOR_ 16-bit vector C_MAX_LAT 8-bit vector C_MIN_GNT 8-bit vector Configuration www.xilinx.com Default VHDL Value Type integer integer NOT_SET string std_logic_ 0x0000 vector std_logic_ 0x0000 vector std_logic_ 0x000000...
  • Page 13 STERS) C_PLB_NUM_ 1-16 MASTERS C_PLB_ 32 (only allowed value AWIDTH C_PLB_ 64 (only allowed value DWIDTH See PLB IPIF data C_FAMILY sheet www.xilinx.com PLB PCI Full Bridge (v1.00a) Default VHDL Value Type integer integer integer integer integer integer integer virtex2...
  • Page 14 PLB Bus PLB Bus PLB Bus PLB Bus PLB Bus PLB Bus PLB Bus PLB Bus PLB Bus PLB Bus PLB Bus PLB Bus PLB Bus PLB Bus PLB Bus PLB Bus www.xilinx.com Description DS508 March 21, 2006 Product Specification...
  • Page 15 PLB Bus PLB Bus PLB Bus PLB Bus PLB Bus PLB Bus Table note 1 applies from P53 to P4. PCI Address and Data Path Signals PCI Bus Time-multiplexed address and data bus www.xilinx.com PLB PCI Full Bridge (v1.00a) Description...
  • Page 16 PCI bus clock signal PCI Bus Internal Arbiter Signals Input from PCI Bus REQ_N available at top-level as Internal output from bridge Input from PCI Bus FRAME_N availalble at top-level Internal as output from bridge www.xilinx.com Description DS508 March 21, 2006 Product Specification...
  • Page 17 Virtex-4 Only, IDELAY Clock 200 MHz clock input to IDELAY elements of Virtex-4 Internal buffers. Ignored if not Virtex-4 architecture. PCI Bus Monitoring Debug Vector Signal Internal Output vector to monitor PCI Bus. www.xilinx.com PLB PCI Full Bridge (v1.00a) Description...
  • Page 18 (IPIF BAR) Meaningful only if G1>2, then G10 to G1 and G11 define the range in PLB-memory space that is responded to by this device (IPIF BAR) www.xilinx.com Description DS508 March 21, 2006 Product Specification...
  • Page 19 (IPIF BAR) G1, G22, Meaningful only if G48 = 0 and G1=6. In G23 and this case only high-order bits that are the same in G22 and G23 are meaningful. Meaningful only if G1=6 www.xilinx.com Description...
  • Page 20 IPIF2PCI FIFO DEPTH-3 where IPIF2PCI FIFO DEPTH given by 2^G36 Must be set to 1 to the lesser of 24 or the IPIF2PCI FIFO DEPTH-1 where IPIF2PCI FIFO DEPTH given by 2^G36 www.xilinx.com Description DS508 March 21, 2006 Product Specification...
  • Page 21 G68=Virtex-4, G52 must include the number of LOC coordinates specified by v3.0 Core Parameters Group Configuration If G61=1, signal P62 has an internal G62, G63, connection and the top-level port P62 has no internal connection www.xilinx.com PLB PCI Full Bridge (v1.00a) Description...
  • Page 22 Name Target Ignore Ignore Ignore Ignore www.xilinx.com Description If G61=0, G62 has no meaning. If G61=1, G62 sets the number of devices supported in configuration operations. Must be sufficiently large to include the address bit defined by G63. If G49=1,...
  • Page 23 C_BASEADDR + 0x110 C_BASEADDR + 0x114 C_BASEADDR + 0x180 C_BASEADDR + 0x184 C_BASEADDR + 0x188 C_BASEADDR + 0x18C C_BASEADDR + 0x190 C_BASEADDR + 0x194 C_BASEADDR + 0x198 www.xilinx.com Table 5. The Registers that reside Access Read/TOW Read/Write Read/Write Read Read/Write...
  • Page 24 Present only if G1>2 and G48=1 Present only if G1>3 and G48=1 Present only if G1>4 and G48=1 Present only if G1=6 and G48=1 Present only if G49=1 in the Processor IP Reference Guide. www.xilinx.com Table DS508 March 21, 2006 Product Specification...
  • Page 25 PCI write retries were not successful due to a PCI 1 to clear retry on the last retry during a PLB Master burst write to a PCI target. www.xilinx.com PLB PCI Full Bridge (v1.00a) Table 7. Unlike most Description...
  • Page 26 PLB Master Burst Write Retry Timeout Enable- Enables this interrupt to be passed to the interrupt controller. Read/Write • 0 - Not enabled. • 1 - Enabled. www.xilinx.com Description Table 9. The interrupt Description DS508 March 21, 2006 Product Specification...
  • Page 27 PLB Master Read SERR Enable- Enables this interrupt to be passed to the interrupt controller. Read/Write • 0 - Not enabled. • 1 - Enabled. Guide. The IP Reset module permits the software reset of the PLB www.xilinx.com PLB PCI Full Bridge (v1.00a) Description...
  • Page 28 Read or write causes automatic execution of Configuration Read Command or Configuration Write Command using address/bus information in the Configuration Address Port register. C_INCLUDE_PCI_CONFIG=1). www.xilinx.com This register is read/write with some bits Description . This register is read/write and definition Description This register is read/write.
  • Page 29 Access Value M+1 high-order bits that are substituted in address Read/Write translation from Nth IPIFBAR access to PCI address space Read Only Low-order bits set to zero www.xilinx.com PLB PCI Full Bridge (v1.00a) Description , the values in the Description...
  • Page 30 The remaining low-order bits are set to zero when a read of these registers is performed. Writing 0x56710000 to IPIFBAR2PCIBAR_0 High-Order Bit Register and then accessing the PLB PCI bridge IPIFBAR_0 with address 0x12340ABC on the PLB bus would yield 0x56710ABC on the PCI bus. www.xilinx.com DS508 March 21, 2006 Product Specification...
  • Page 31 Table 14 shows specifics of the data format. The Reset Access Value Read Only Set to zero. Defines the device number of the PLB PCI bridge when Read/Write configured as a Host Bridge. www.xilinx.com PLB PCI Full Bridge (v1.00a) Description...
  • Page 32 PCI I/O Space PCI Memory Space Prefetchable or Prefetchable Non-prefetchable I/O Read Memory Read I/O Read Memory Read Multiple www.xilinx.com Table 15 shows the shows the translations of PCI PCI Memory Space Non-prefetchable Not Supported Not Supported DS508 March 21, 2006...
  • Page 33 FIFO PLB Burst Write contiguous blocks on the PCI side. Up to three independent blocks are range, and address translation vector. Only memory space in the sense www.xilinx.com PLB PCI Full Bridge (v1.00a) Not Supported Not Supported...
  • Page 34 • If the target PCI address space is memory space, the 2 lsbs are set to 00 (i.e., linear incrementing The PLB IPIF and bridge can accept both fixed length and arbitrary PLB_rdBurst signal) burst transactions on the PLB. Table 15 www.xilinx.com Only one shows translations of PLB DS508 March 21, 2006 Product Specification...
  • Page 35 Because the data is required to be prefetchable, data is not lost when the FIFO is flushed. Dynamic byte enable is not supported in Xilinx PLB burst operations and is not supported in the PLB Master read of a PCI target. All byte enable bits are asserted in PLB master burst read operations.
  • Page 36 PLB address incrementing beyond a valid range on a burst, hence, the request can continue when the FIFO is empty. If this occurs, the bridge will allow an IPIF timeout to occur. When an IPIF timeout occurs, Slv_MErr is asserted by the IPIF. www.xilinx.com DS508 March 21, 2006 Product Specification...
  • Page 37 Immediately allow PLB IPIF timeout which results in Slv_MErr being asserted and set the PLB Target Abort Master Read interrupt www.xilinx.com PLB PCI Full Bridge (v1.00a) Burst (PLB_rdBurst asserted) IPIF timeout and Slv_MErr is asserted (most cases; see above...
  • Page 38 The PLB PCI Bridge will transfer the data on the PCI if it is received without error flagging. It is the user’s responsibility not to . The PLB specification requires all PLB_wrBurst PLB_wrBurst www.xilinx.com is asserted. DS508 March 21, 2006 Product Specification...
  • Page 39 • If on a burst transfer, the initiator latency timer expires, the PLB PCI Bridge terminates the PCI DS508 March 21, 2006 Product Specification is asserted with . The IPIF2PCI FIFO is flushed Sl_MErr Sl_wrDAck www.xilinx.com PLB PCI Full Bridge (v1.00a)
  • Page 40 Disconnect with(out) Data, the PLB Master Write Retry Disconnect interrupt is asserted. PLB Master Write PERR interrupt asserted. If the burst write is still in progress, Sl_MErr is asserted with Sl_wrDAck. FIFO is flushed. www.xilinx.com Burst (PLB_wrBurst asserted) DS508 March 21, 2006 Product Specification...
  • Page 41 The lsbs are set to the lowest address of the byte lane asserted in the byte enable vector as required by the Xilinx PLB specification. Byte enables from the PCI bus are passed correctly to the PLB in single PLB read transactions.
  • Page 42 PCI data flow is very different for read multiple commands depending on the relative clock speeds. If the PLB clock is faster, the data flow is limited by the PCI bus and the data flow is, in most cases, one continuous read multiple. www.xilinx.com DS508 March 21, 2006 Product Specification...
  • Page 43 Table 19 summarizes most PLB slave abnormal conditions in a memory read command and how the response is translated to the PCI initiator. DS508 March 21, 2006 Product Specification PLB PCI Full Bridge (v1.00a) which terminates the PLB PLB_MRdBTerm www.xilinx.com...
  • Page 44 FIFO full. Disconnect with data on the last valid address on the PCI bus. If the parameterized number of double words are received, the www.xilinx.com Memory Read Multiple DS508 March 21, 2006 Product Specification...
  • Page 45 PCI initiator writes are inhibited. Target disconnects without data (PCI retry) will be asserted for subsequent PCI transactions when the transactions are DS508 March 21, 2006 Product Specification will be set at build time and is an C_NUM_IPIF_RETRIES_IN_WRITES www.xilinx.com PLB PCI Full Bridge (v1.00a) inhibited.If the...
  • Page 46 Automatically retried a parameterized number of times for each PCI write command. If the retries fail, the PCI interrupt is strobed Accept data from only valid address on the PCI bus. Disconnect to terminate the PCI transaction. www.xilinx.com and assert PLB-side and terminate PLB DS508 March 21, 2006...
  • Page 47 Latency timer, BAR0, BAR1, and BAR2 are required to be set by the host bridge as necessary. The number of BARs (0-3) is set by the parameter C_PCIBAR_NUM. The User Configuration Space is enabled for the LogiCORE v3.0 implementation used in the PLB PCI bridge. DS508 March 21, 2006 Product Specification PLB PCI Full Bridge (v1.00a) www.xilinx.com...
  • Page 48 Results in Latency Timer Register after write (PLB-side byte swapped format) by remote host bridge by self-configuration 0x00 0x01 0xFF Table 5. The registers exist only if the bridge is www.xilinx.com 0x4605 0x4605 0x4605 0x4605 0x4605 0x4605 0x4605 0x4605 0x4605...
  • Page 49 The unique set of configuration registers are used to perform configuration accesses on the unique primary PCI bus and its’ DS508 March 21, 2006 Product Specification PLB PCI Full Bridge (v1.00a) www.xilinx.com...
  • Page 50 Xilinx XST and Synplicity’s Synplify Pro synthesis tools are used for synthesizing the PLB PCI Bridge. The NGC format from XST and EDIF netlist output from Synplify Pro are then input to the Xilinx Alliance tool suite for actual device implementation.
  • Page 51 PCI Transaction Control Signals FRAME_N DEVSEL_N TRDY_N IRDY_N STOP_N IDSEL PCI Interrupt Signals INTR_A PCI Error Signals PERR_N SERR_N PCI Arbitration Signals REQ_N GNT_N PCI Address, Data Path, and Command Signals AD[31:0] CBE[3:0] www.xilinx.com PLB PCI Full Bridge (v1.00a) Instantiated IO-Buffer Optional Optional...
  • Page 52 NET "PCI_FRAME_N" NET "PCI_TRDY_N" NET "PCI_IRDY_N" NET "PCI_STOP_N" NET "PCI_DEVSEL_N" BYPASS; NET "PCI_PERR_N" NET "PCI_SERR_N" IOSTANDARD=PCI33_3; IOSTANDARD=PCI33_3; IOSTANDARD=PCI33_3; IOSTANDARD=PCI33_3; IOSTANDARD=PCI33_3; IOSTANDARD=PCI33_3; IOSTANDARD=PCI33_3; IOSTANDARD=PCI33_3; IOSTANDARD=PCI33_3; BYPASS; BYPASS; BYPASS; BYPASS; BYPASS; BYPASS; BYPASS; BYPASS; BYPASS; www.xilinx.com DS508 March 21, 2006 Product Specification...
  • Page 53 11.000 ns 7.000 ns 10.000 ns 28.000 ns 30.000 ns 7.000 VALID 7.000 BEFORE "PCI_CLK" TIMEGRP 7.000 VALID 7.000 BEFORE "PCI_CLK" TIMEGRP 7.000 VALID 7.000 BEFORE "PCI_CLK" TIMEGRP 7.000 VALID 7.000 BEFORE "PCI_CLK" TIMEGRP www.xilinx.com PLB PCI Full Bridge (v1.00a)
  • Page 54 IDELAYCTRL. This is required for EDK 8.1 tools because when instantiating only "PCI_CLK" TIMEGRP "FAST_FFS" ; "PCI_CLK" TIMEGRP "FAST_FFS" ; "PCI_CLK" TIMEGRP "FAST_FFS" ; "PCI_CLK" TIMEGRP "ALL_FFS" "PCI_CLK" TIMEGRP "SLOW_FFS" ; "PCI_CLK" TIMEGRP "SLOW_FFS" ; "PCI_CLK" TIMEGRP "SLOW_FFS" ; www.xilinx.com DS508 March 21, 2006 Product Specification...
  • Page 55 An example of the syntax for the C_IDELAYCTRL_LOC parameter is shown below. DS508 March 21, 2006 Product Specification Virtex-4 User Guide discussion of IDELAYCTRL usage and design guidance www.xilinx.com PLB PCI Full Bridge (v1.00a) Virtex-4 User Guide discussion of...
  • Page 56 IOBDELAY_TYPE=VARIABLE ; IOBDELAY_TYPE=VARIABLE ; IOBDELAY_TYPE=VARIABLE ; IOBDELAY_TYPE=VARIABLE ; IOBDELAY_TYPE=VARIABLE ; IOBDELAY_VALUE=55 ; IOBDELAY_VALUE=55 ; IOBDELAY_VALUE=55 ; IOBDELAY_VALUE=55 ; IOBDELAY_VALUE=55 ; IOBDELAY_VALUE=55 ; IOBDELAY_VALUE=55 ; IOBDELAY_VALUE=55 ; IOBDELAY_VALUE=55 ; IOBDELAY_VALUE=55 ; IOBDELAY_VALUE=55 ; IOBDELAY_VALUE=55 ; www.xilinx.com DS508 March 21, 2006 Product Specification...
  • Page 57 Parameter Values Device Resources 3336 2961 3163 2729 3163 2805 2976 2573 3181 2851 2962 2684 www.xilinx.com PLB PCI Full Bridge (v1.00a) 25. The data is shown for a Virtex-II Pro 3868 >100 3695 >100 3615 >100 3442 >100 3667 >100 3352 >100...

  • Page 58: Reference Documents

    The following documents contain reference information important to understanding the PLB PCI Bridge design: • Processor IP Reference Guide • Xilinx LogiCORE PCI Interface v3.0 Product Specification • Xilinx The Real-PCI Design Guide v3.0 • IPSPECXXX PLB IPIF/LogiCore v3.0 PCI Core Bridge Verification Plan •...