Dsp48E1 Slice Primitive - Xilinx 7 Series User Manual

DSP48E1 Slice Primitive

Figure 2-4
DSP48E1 slice along with the bit width of each port. The port definitions are in
X-Ref Target - Figure 2-4
7 Series DSP48E1 User Guide
UG479 (v1.10) March 27, 2018
shows the DSP48E1 primitive. It also shows the input and output ports of the
30
A[29:0]
18
B[17:0]
48
C[47:0]
25
D[24:0]
7
OPMODE[6:0]
4
ALUMODE[3:0]
CARRYIN
3
CARRYINSEL[2:0]
5
INMODE[4:0]
CEA 1
CEA 2
CEB 1
CEB 2
CEC
CED
CEM
CEP
CEAD
CEALUMODE
CECTRL
CECARRYIN
CEINMODE
RSTA
RSTB
RSTC
RSTD
RSTM
RSTP
RSTCTRL
RSTALLCARRYIN
RSTALUMODE
RSTINMODE
CLK
30
ACIN[29:0]
18
BCIN[17:0]
48
PCIN[47:0]
CARRYCASCIN
MULTSIGNIN
Figure 2-4: DSP48E1 Slice Primitive
www.xilinx.com
DSP48E1 Slice Primitive
ACOUT[29:0]
BCOUT[17:0]
PCOUT[47:0]
P[47:0]
CARRYOUT[3:0]
CARRYCASCOUT
MULTSIGNOUT
PATTERNDETECT
PATTERNBDETECT
OVERFLOW
UNDERFLOW
UG369_c1_04_051209
Send Feedback
Table 2-2.
30
18
48
48
4
21