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SelectIO Logic Resources
Introduction
This chapter describes the logic directly behind the I/O drivers and receivers covered in
Chapter 1, SelectIO
7 series FPGAs contain the basic I/O logic resources from previous Xilinx FPGAs. These
resources include the following:
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Figure 2-1
3.3V HR bank. The SelectIO™ input, output, and 3-state drivers are in the input/output
buffer (IOB). The HP banks have separate IDELAY and ODELAY blocks. The HR bank has
the same logic elements as the HP banks except for the ODELAY block.
X-Ref Target - Figure 2-1
7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
Resources.
Combinatorial input/output
3-state output control
Registered input/output
Registered 3-state output control
Double-Data-Rate (DDR) input/output
DDR output 3-state control
IDELAY provides users control of an adjustable, fine-resolution delay taps
ODELAY provides users control of an adjustable, fine-resolution delay taps
SAME_EDGE output DDR mode
SAME_EDGE and SAME_EDGE_PIPELINED input DDR mode
shows a I/O tile for the 1.8V HP banks.
PAD
Figure 2-1: 7 Series FPGA HP Bank I/O Tile
www.xilinx.com
Figure 2-2
IDELAYE2
IOB
ODELAYE2
Chapter 2
shows an I/O tile for a
ILOGICE2/
ISERDESE2
OLOGICE2/
OSERDESE2
UG471_c1_01_012211
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