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Chapter 3:
Advanced SelectIO Logic Resources
Table 3-17: OUT_FIFO Input to Output Data Mapping
Both modes support the FULL, EMPTY, ALMOSTFULL, and ALMOSTEMPTY flags.
OUT_FIFO Primitive
The OUT_FIFO primitive is shown in
178
Send Feedback
used when the output clock frequency is twice the input clock frequency and thus
output data is half the width of the input data.
mapping in detail.
Mapping
D0[7:0] → Q0[3:0]
D1[7:0] → Q1[3:0]
D2[7:0] → Q2[3:0]
D3[7:0] → Q3[3:0]
D4[7:0] → Q4[3:0]
D5[7:0] → Q5[3:0]
D6[7:0] → Q6[3:0]
D7[7:0] → Q7[3:0]
D8[7:0] → Q8[3:0]
D9[7:0] → Q9[3:0]
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Table 3-17
shows the 8 x 4 mode
Not Used
Figure
3-21.
7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
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