Xilinx SelectIO 7 Series User Manual page 75

bidirectional signals (no input-only or output-only). HR banks provide IN_TERM options
for untuned internal parallel split-termination resistors. Although the optimal drive and
termination scheme for any new design is determined through careful signal-integrity
analysis, initial considerations include:
•
•
SSTL135 is used for DDR3L SDRAM memory interfaces and is roughly defined (not by
name) in the JEDEC standard JESD79-3-1. For this standard, the full-strength driver
(SSTL135) is available in both the HP and HR I/O banks. A weaker, reduced-strength
driver, designated by an R in the standard name (SSTL135_R), is available in the HR I/O
banks. Both drivers support bidirectional and unidirectional signaling. For some
topologies (such as short point-to-point interfaces), the reduced-strength driver can result
in reduced overshoot and better signal integrity.
The HP I/O banks also provide DCI and T_DCI options for tuned internal parallel
split-termination resistors. While the DCI option is not available for bidirectional signals
(input or output only), the T_DCI option is only available for bidirectional signals (no
input-only or output-only). HR banks provide IN_TERM options for untuned internal
parallel split-termination resistors. Although the optimal drive and termination scheme
for any new design is determined through careful signal-integrity analysis, initial
considerations include:
•
•
SSTL12 supports Micron's next-generation RLDRAM3 memory. This standard is only
available in the HP I/O banks. Both DCI and T_DCI options are available to improve the
signal integrity through the use of tuned internal split-termination resistors. While the DCI
option is not available for bidirectional signals (input or output only), the T_DCI option is
only available for bidirectional signals (no input-only or output-only). Although the
optimal drive and termination scheme for any new design is determined through careful
signal-integrity analysis, initial considerations include:
•
•
•
7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
HP I/O banks: SSTL15_T_DCI at the 7 series FPGAs bidirectional pins (DQ and DQS),
and SSTL15 at the unidirectional pins (all other pins). ODT used at the memory device
on the bidirectional signals, and external parallel-termination resistors to
V = V /2 for the unidirectional signals.
TT CCO
HR I/O banks: SSTL15 at the 7 series FPGAs pins for both bidirectional (DQ/DQS)
and unidirectional (all other pins) signals, combined with the IN_TERM (internal
termination) attribute on the bidirectional pins. Use ODT at the memory device on the
bidirectional signals, and external parallel-termination resistors to V
the unidirectional signals.
HP I/O banks: SSTL135_T_DCI at the 7 series FPGAs bidirectional pins (DQ and
DQS), and SSTL135 at the unidirectional pins (all other pins). ODT used at the
memory device on the bidirectional signals, and external parallel-termination
resistors to V = V /2 for the unidirectional signals.
TT CCO
HR I/O banks: SSTL135 at the 7 series FPGAs pins for both bidirectional (DQ/DQS)
and unidirectional (all other pins) signals, combined with the IN_TERM (internal
termination) attribute on the bidirectional pins. Use ODT at the memory device on the
bidirectional signals, and external parallel-termination resistors to V
the unidirectional signals.
SSTL12_T_DCI at the 7 series FPGAs bidirectional pins (DQ and DQS)
SSTL12 at the unidirectional pins (all other pins).
ODT used at the memory device, if available on the bidirectional signals, and external
parallel-termination resistors to V
www.xilinx.com
Supported I/O Standards and Terminations
= V /2 where ODT is not available.
TT CCO
= V /2 for
TT CCO
= V /2 for
TT CCO
75
Send Feedback