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Chapter 1:
SelectIO Resources
Supply Voltages for the SelectIO Pins
V
The V
columns in
standards, and illustrate the V
optional internal differential termination circuit. All V
be connected to the same external voltage supply on the board, and as a result all of the
I/O within a given I/O bank must share the same V
match the requirements for the I/O standards that have been assigned to the I/O bank. An
incorrect V
7 series power supply requirements, including power-on and power-off sequencing, are
described in the 7 series FPGA data sheets.
In HP I/O banks, if the I/O standard voltage requirement is < 1.8V, but a V
applied, the device automatically enters an overvoltage protection mode. Reconfiguring
the device with the correct V
V
Single-ended I/O standards with a differential input buffer require an input reference
voltage (V
pins for the bank must be used as V
internally generated reference voltage by enabling the INTERNAL_VREF constraint. For
more information on this constraint, see
page
V
The global auxiliary (V
various block feature's interconnect logic inside the 7 series FPGAs. In the I/O banks,
V
include all of the single-ended I/O standards at or below 1.8V, and also some of the 2.5V
standards (HR I/O banks only). Additionally, the V
bank's differential input buffer circuits used for the differential and V
The 7 series power supply requirements, including power-on and power-off sequencing,
are described in the 7 series FPGA data sheets.
V
The auxiliary I/O (V
power to the I/O circuitry. The Kintex-7 and Virtex-7 FPGAs data sheets contain a table
titled Maximum Physical Interface (PHY) Rate for Memory Interfaces that references
V
(default), or optionally at 2.0V to achieve higher frequency performance for certain types
of memory interfaces. Although this table is designed for memory interfaces, it can also
provide guidance on powering V
based on the target bit rates. The table does not apply to LVDS, which uses a different type
of driver circuit than the single-ended drivers that are more affected by the V
level. Thus, for LVDS interfaces, it does not matter which voltage level the V
is powered at. The default value of 1.8V affords a lower-power consumption and provides
very close to the same performance in the I/Os. The 2.0V option is available when the
slightly-increased performance is required for the very fastest bit rates supported for the
single-ended drivers.
18
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CCO
supply is the primary power supply of the 7 series I/O circuitry. The
CCO
Table 1-55
provide the V
voltage can result in loss of functionality or damage to the device. The
CCO
REF
). When V
REF
REF
46.
CCAUX
CCAUX
is also used to power input buffer circuits for some of the I/O standards. These
CCAUX
CCAUX_IO
CCAUX_IO
. This table indicates how the V
CCAUX_IO
www.xilinx.com
requirements for each of the supported I/O
CCO
requirements for both inputs and outputs as well as the
CCO
CCO
level restores normal operation.
CCO
is required within an I/O bank, the two multi-function V
supply inputs. 7 series FPGAs can optionally use an
REF
7 Series FPGA SelectIO Attributes/Constraints,
) supply rail is primarily used for providing power to the
CCAUX
) supply rail is only present in HP I/O banks and provides
pins can be powered at either 1.8V
CCAUX_IO
for other high-speed single-ended interfaces
CCAUX_IO
7 Series FPGAs SelectIO Resources User Guide
pins for a given I/O bank must
CCO
level. The V
voltage must
CCO
CCO
rail provides power to the
I/O standards.
REF
CCAUX_IO
CCAUX_IO
UG471 (v1.10) May 8, 2018
V
CCO (V)
> 2.5V is
REF
rail
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