Selectio Resources Introduction - Xilinx SelectIO 7 Series User Manual

SelectIO Resources Introduction

All 7 series FPGAs have configurable SelectIO drivers and receivers, supporting a wide
variety of standard interfaces. The robust feature set includes programmable control of
output strength and slew rate, on-chip termination using digitally-controlled impedance
(DCI), and the ability to internally generate a reference voltage (INTERNAL_VREF).
Note:
to the HR banks.
With some exceptions, each I/O bank contains 50 SelectIO pins. The two pins at the very
ends of each bank can only be used with single-ended I/O standards. The remaining 48
pins can be used with either single-ended or differential standards using two SelectIO pins
grouped together as positive/negative (P/N) pairs. Every SelectIO resource contains
input, output, and 3-state drivers.
The SelectIO pins can be configured to various I/O standards, both single-ended and
differential.
•
•
Figure 1-1
internal logic and the device pad.
the single-ended (only) HR IOB.
HR I/O banks, the single-ended (only) and regular IOBs are essentially equivalent, except
the single-ended (only) IOBs do not have the connections to make the differential output
signals. In most devices, the single-ended (only) IOBs are the two pins located at the ends
of each I/O bank. The regular IOB that make up the other 48 pins in each bank can
implement both single-ended and differential I/O standards.
Each IOB has a direct connection to an ILOGIC/OLOGIC pair containing the input and
output logic resources for data and 3-state control for the IOB. Both ILOGIC and OLOGIC
can be configured as ISERDES and OSERDES, respectively, as described in
Advanced SelectIO Logic
X-Ref Target - Figure 1-1
DCITERMDISABLE
7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
HR banks do not have DCI. Therefore, any reference to DCI in this user guide does not apply
Single-ended I/O standards (e.g., LVCMOS, LVTTL, HSTL, PCI, and SSTL)
Differential I/O standards (e.g., LVDS, Mini_LVDS, RSDS, PPDS, BLVDS, and
differential HSTL and SSTL)
shows the single-ended (only) HP I/O block (IOB) and its connections to the
Resources.
T
O
DIFFI_IN
IBUFDISABLE
Figure 1-1: Single-Ended (Only) HP IOB Diagram
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SelectIO Resources Introduction
Figure 1-2 shows the regular HP IOB.
Figure 1-4 shows the regular HR IOB. In both the HP and
PAD
Figure 1-3 shows
Chapter 3,
PADOUT
I
UG471_c1_03_010711
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