Xilinx MIcroBlaze Development Spartan-3E 1600E Kit User Manual
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Xilinx MIcroBlaze Development Spartan-3E 1600E Kit User Manual

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MicroBlaze Development
Kit Spartan-3E 1600E
Edition User Guide
UG257 (v1.1) December 5, 2007
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Summary of Contents for Xilinx MIcroBlaze Development Spartan-3E 1600E Kit

  • Page 1 MicroBlaze Development Kit Spartan-3E 1600E Edition User Guide UG257 (v1.1) December 5, 2007...

  • Page 2: Revision History

    Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design.

  • Page 3: Table Of Contents

    Spartan-3E FPGA Features and Embedded Processing Functions ....9 Learning Xilinx FPGA, CPLD, and ISE Development Software Basics ... . . 9 Advanced Spartan-3 Generation Development Boards .
  • Page 4 ............. 67 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...
  • Page 5 Xilinx XC2C64A CPLD ........
  • Page 6 CPLD ..............129 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...
  • Page 7 ..... 156 DDR SDRAM Series Termination and FX2 Connector Differential Termination Appendix B: Example User Constraints File (UCF) MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...
  • Page 8 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...

  • Page 9: Preface: About This Guide

    Spartan™-3E Starter Kit Board Reference Page http://www.xilinx.com/sp3e1600e Acknowledgements Xilinx wishes to thank the following companies for their support of the MicroBlaze Development Kit board: Intel Corporation for the 128 Mbit StrataFlash memory Linear Technology for the SPI-compatible A/D and D/A converters, the...

  • Page 10: Additional Resources

    Appendix B, “Example User Constraints File (UCF),” provides example code from a UCF. Additional Resources To find addtional resources for the MicroBlaze Processor or the Xilinx Embedded development tools, see the Xilinx website at: http://www.Xilinx.com/Microblaze http://www.Xilinx.com/EDK To find additional documentation, see the Xilinx website at: http://www.xilinx.com/literature.

  • Page 11: Chapter 1: Introduction And Overview

    Edition. You will find it useful in developing your Spartan-3E FPGA application. Choose the Starter Kit Board for Your Needs Depending on specific requirements, choose the Xilinx development board that best suits your needs. Spartan-3E FPGA Features and Embedded Processing Functions...

  • Page 12: Key Components And Features

    Chapter 1: Introduction and Overview http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=DO- ML403-EDK-ISE Also consider the capable boards offered by Xilinx partners: http://www.xilinx.com/products/devboards/index.htm Key Components and Features The key features of the MicroBlaze Development Kit board are: Xilinx XC3S1600E Spartan-3E FPGA Up to 250 user-I/O pins...

  • Page 13: Design Trade-Offs

    The on-chip circuitry simplifies the device programming experience. In typical applications, the JTAG programming hardware resides off-board or in a separate programming module, such as the Xilinx Platform USB cable. This USB port is for programming only and can not be used as an independent USB interface.
  • Page 14 Chapter 1: Introduction and Overview MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...

  • Page 15: Chapter 2: Switches, Buttons, And Knob

    I/O standard used. The PULLUP resistor is not required, but it defines the input value when the switch is in the middle of a transition. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...

  • Page 16: Push-Button Switches

    Figure 2-5 shows how to specify a pull-down resistor within the UCF. There is no active debouncing circuitry on the push button. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...

  • Page 17: Ucf Location Constraints

    Low. Figure 2-9 shows how to specify a pull-down resistor within the UCF. There is no active debouncing circuitry on the push button. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...
  • Page 18 See the Rotary Encoder Interface reference design in“Related Resources” for an example. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...

  • Page 19: Ucf Location Constraints

    The MicroBlaze Development Kit board has eight individual surface-mount LEDs located above the slide switches as shown in Figure 2-10. The LEDs are labeled LED7 through LED0. LED7 is the left-most LED, LED0 the right-most LED. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...

  • Page 20: Operation

    NET "LED<0>" LOC = "D4” | IOSTANDARD = SSTL2_I ; UG257_02_11_062106 Figure 2-11: UCF Constraints for Eight Discrete LEDs Related Resources Rotary Encoder Interface for Spartan-3E Starter Kit (Reference Design) http://www.xilinx.com/s3estarter http://www.xilinx.com/sp3e1600E MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...

  • Page 21: Chapter 3: Clock Sources

    As shown in Figure 3-1, the MicroBlaze Development Kit board supports three primary clock input sources, all of which are located below the Xilinx logo, near the Spartan-3E logo. The board includes an on-board 50 MHz clock oscillator. The user clock socket is populated with a 66 MHz oscillator Clocks can be supplied off-board via an SMA-style connector.

  • Page 22: Clock Connections

    I/O pin assignments and I/O standards. The period constraints define the clock period—and consequently the clock frequency—and the duty cycle of the incoming clock signal. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...

  • Page 23: Location

    UG257_03_02_061306 Figure 3-2: UCF Location Constraints for Clock Sources Clock Period Constraints The Xilinx ISE development software uses timing-driven logic placement and routing. Set the clock PERIOD constraint as appropriate. An example constraint appears in Figure 3-3 for the on-board 50 MHz clock oscillator. The CLK_50MHZ frequency is 50 MHz, which equates to a 20 ns period.
  • Page 24 Chapter 3: Clock Sources MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...

  • Page 25: Chapter 4: Fpga Configuration Options

    Download FPGA designs directly to the Spartan-3E FPGA via JTAG, using the on- board USB interface. The on-board USB-JTAG logic also provides in-system programming for the on-board Platform Flash PROM and the Xilinx XC2C64A CPLD. SPI serial Flash and StrataFlash programming are performed separately.
  • Page 26 DONE Pin LED Spartan-3E Lights up when FPGA successfully configured Development Board 4 Mbit Xilinx Platform Flash PROM Configuration storage for Master Serial mode (one XC04S on front and one on the back of the board” 64 Macrocell Xilinx XC2C64A CoolRunner CPLD...

  • Page 27: Configuration Mode Jumpers

    The DONE pin LED lights when the FPGA successfully finishes configuration. Pressing the PROG button forces the FPGA to restart its configuration process. The 4 Mbit Xilinx Platform Flash PROM provides easy, JTAG-programmable configuration storage for the FPGA. The FPGA configures from the Platform Flash using Master Serial mode.

  • Page 28: Prog Push Button

    The DONE pin LED, shown in Figure 4-2, page 24, lights whenever the FPGA is successfully configured. If this LED is not lit, then the FPGA is not configured. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...

  • Page 29: Programming The Fpga, Cpld, Or Platform Flash Prom Via Usb

    Figure 4-3: Standard USB Type A/Type B Cable The wider and narrower Type A connector fits the USB connector at the back of the computer. After installing the Xilinx software, connect the square Type B connector to the MicroBlaze Development Kit board, as shown in Figure 4-4.

  • Page 30: Programming Via Impact

    PC, a green LED lights up, indicating a good connection. Programming via iMPACT After successfully compiling an FPGA design using the Xilinx development software, the design can be downloaded using the iMPACT programming software and the USB cable. To begin programming, connect the USB cable to the starter kit board and apply power to the board.
  • Page 31 When the FPGA successfully programs, the iMPACT software indicates success, as shown Figure 4-9. The FPGA application is now executing on the board and the DONE pin LED (see Figure 4-2) lights up. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...

  • Page 32: Programming Platform Flash Prom Via Usb

    CCLK oscillator always starts at its slowest setting, approximately 1.5 MHz. Most external PROMs support a higher frequency. Increase the CCLK frequency as appropriate to reduce the FPGA’s configuration time. The Xilinx XCF04S Platform Flash supports a 25 MHz CCLK frequency.
  • Page 33 25 MHz, the fastest frequency when using an XCF04S Platform Flash PROM. Click OK when finished. UG257_04_11_061206 Figure 4-11: Set CCLK Configuration Rate under Configuration Options MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...
  • Page 34 Figure 4-13. UG257_04_13_061206 Figure 4-13: Double-Click Generate PROM, ACE, or JTAG File After iMPACT starts, double-click PROM File Formatter, as shown in Figure 4-14. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...
  • Page 35 Programming the FPGA, CPLD, or Platform Flash PROM via USB UG257_04_14_061206 Figure 4-14: Double-Click PROM File Formatter Choose Xilinx PROM as the target PROM type, as shown in Figure 4-15. Select from any of the PROM File Formats; the Intel Hex format (MCS) is popular. Enter the Location of the directory and the PROM File Name.
  • Page 36 Figure 4-16: Choose the XCF04S Platform Flash PROM The PROM Formatter then echoes the settings, as shown in Figure 4-17. Click Finish. UG257_4-17_061206 Figure 4-17: Click Finish after Entering PROM Formatter Settings MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...
  • Page 37 PROM, the select FPGA bitstream(s), and the amount of PROM space consumed by the bitstream. Figure 4-19 shows an example for a single XC3S500E FPGA bitstream stored in an XCF04S Platform Flash PROM. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...
  • Page 38 Figure 4-20: Click Operations Generate File to Create the Formatted PROM File The iMPACT software indicates that the PROM file was successfully created, as shown in Figure 4-21. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...
  • Page 39 Boundary Scan in the iMPACT Modes pane, as shown in Figure 4-22, or by clicking on the Boundary Scan tab. UG257_04_22_061206 Figure 4-22: Switch to Boundary Scan Mode MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...
  • Page 40 The programming software again prompts for the PROM type to be programmed. Select xcf04s and click OK, as shown in Figure 4-25. UG257_04_25_061206 Figure 4-25: Select XCF04S Platform Flash PROM MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...
  • Page 41 FPGA to reconfigure from the newly programmed Platform Flash PROM. If the FPGA successfully configures, the DONE LED, also shown in Figure 4-2, lights up. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...
  • Page 42 Chapter 4: FPGA Configuration Options MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...

  • Page 43: Overview

    SF_D10 (P17) SF_D11 (M15) SF_D12 (M16) SF_D13 (P6) SF_D14 (R8) SF_D15 (T8) LCD_CS1 (P3) LCD_CS2 (P4) Intel StrataFlash D[15:8] SF_CEO UG257_05_01_062106 Figure 5-1: Character LCD Interface MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...

  • Page 44: Character Lcd Interface Signals

    StrataFlash I/O pins when the character LCD drives a High logic value. The character LCD drives the data lines when LCD_RW is High. Most applications treat the LCD as a write- only peripheral and never read from from the display. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...

  • Page 45: Interaction With Intel Strataflash

    NET "SF_D<15>" LOC = "T8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; UG257_05_02_061306 Figure 5-2: UCF Location Constraints for the Character LCD MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...

  • Page 46: Lcd Controller

    CG ROM. For example, a hexadecimal character code of 0x53 stored in a DD RAM location displays the character ‘S’. The upper nibble of 0x53 equates to DB[7:4]=”0101” MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...
  • Page 47 CG RAM. Write CG RAM data using the Write Data to CG RAM or DD RAM command, and read CG RAM using the Read Data from CG RAM or DD RAM command. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...

  • Page 48: Command Set

    Table 5-3: LCD Character Display Command Set Upper Nibble Lower Nibble Function Clear Display Return Cursor Home Entry Mode Set Display On/Off Cursor and Display Shift S/C R/L Function Set MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...
  • Page 49 These operations are performed during data reads and writes. Execution Time: 40 s Bit DB1: (I/D) Increment/Decrement Auto-decrement address counter. Cursor/blink moves to left. Auto-increment address counter. Cursor/blink moves to right. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...
  • Page 50 When the displayed data is shifted repeatedly, both lines move horizontally. The second display line does not shift into the first display line. Execution Time: 40 s MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...
  • Page 51 Write data into DD RAM if the command follows a previous Set DD RAM Address command, or write data into CG RAM if the command follows a previous Set CG RAM Address command. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...

  • Page 52: Operation

    230 ns 40 ns 10 ns Upper Lower 4 bits 4 bits LCD_RS SF_D[11:8] LCD_RW LCD_E 1 µs 40 µs UG257_05_06_061406 Figure 5-6: Character LCD Interface Timing MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...

  • Page 53: Transferring 8-Bit Data Over The 4-Bit Interface

    0x06, to set the display to automatically increment the address pointer. Issue a Display On/Off command, 0x0C, to turn the display on and disables the cursor and blinking. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...

  • Page 54: Writing Data To The Display

    Also drive the LCD_RW pin Low to prevent the LCD screen from presenting data. Related Resources Initial Design for Spartan-3E MicroBlaze Development Kit (Reference Design) http://www.xilinx.com/s3e1600e PowerTip PC1602-D Character LCD (Basic Electrical and Mechanical Data) http://www.powertipusa.com/pdf/pc1602d.pdf Sitronix ST7066U Character LCD Controller http://www.sitronix.com.tw/sitronix/product.nsf/Doc/ST7066U?OpenDocument...

  • Page 55: Chapter 6: Vga Display Port

    VGA-specified 0V to 0.7V range. The VGA_HSYNC and VGA_VSYNC signals using LVTTL or LVCMOS33 I/O standard drive levels. Drive MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...

  • Page 56: Signal Timing For A 60 Hz, 640X480 Vga Display

    Much of the potential display time is therefore lost in blanking periods when the beam is reset and stabilized to begin a new horizontal or vertical display pass. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...
  • Page 57 The pixel clock defines the time available to display one pixel of information. The VS signal defines the refresh frequency of the display, or the frequency at which all information on the MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...

  • Page 58: Vga Signal Timing

    No time relationship is specified between the onset of the HS pulse and the onset of the VS pulse. Consequently, the counters can be arranged to easily form video RAM addresses, or to minimize decoding logic for sync pulse generation. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...

  • Page 59: Ucf Location Constraints

    NET "VGA_VSYNC" LOC = "F14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; UG257_06_04_060506 Figure 6-4: UCF Constraints for VGA Display Port Related Resources VESA http://www.vesa.org VGA timing information http://www.epanorama.net/documents/pc/vga_timing.html MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...
  • Page 60 Chapter 6: VGA Display Port MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...

  • Page 61: Overview

    Hardware flow control is not supported on the connector. The port’s DCD, DTR, and DSR signals connect together, as shown in Figure 7-1. Similarly, the port’s RTS and CTS signals connect together. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...
  • Page 62 Serial cable To DTE To DCE Female DB9 Male DB9 RS-232 Voltage Translator (IC2) (R7) (M14) (U8) (M13) Spartan-3E FPGA UG257_07_01_060506 Figure 7-1: RS-232 Serial Ports MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...

  • Page 63: Ucf Location Constraints

    NET "RS232_DCE_TXD" LOC = "M14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; UG257_07_03_060506 Figure 7-3: UCF Location Constraints for DCE RS-232 Serial Port MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...
  • Page 64 Chapter 7: RS-232 Serial Ports MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...

  • Page 65: Chapter 8: Ps/2 Mouse/Keyboard Port

    UG257_08_01_061406 Figure 8-1: PS/2 Connector Location and Signals Table 8-1: PS/2 Connector Pinout PS/2 DIN Pin Signal FPGA Pin DATA (PS2_DATA) Reserved — CLK (PS2_CLK) Reserved MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...

  • Page 66: Keyboard

    The keyboard sends the same scan code, regardless if a key has different shift and non-shift characters and regardless whether the Shift key is pressed or not. The host determines which character is intended. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...
  • Page 67 The clock line can be used as a clear to send signal. If the host pulls the clock line Low, the keyboard must not send any data until the clock is released. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...

  • Page 68: Mouse

    The magnitude of the X and Y values represent the rate of mouse movement. The larger the value, the faster the mouse is moving. The XV and YV bits in the status byte indicate when MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...

  • Page 69: Voltage Supply

    NET "PS2_DATA" LOC = "G13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; U257_08_06_060506 Figure 8-6: UCF Location Constraints for PS/2 Port Related Resources PS/2 Mouse/Keyboard Protocol http://www.computer-engineering.org/ps2protocol/ PS/2 Keyboard Interface http://www.computer-engineering.org/ps2keyboard/ PS/2 Mouse Interface http://www.computer-engineering.org/ps2mouse/ MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...
  • Page 70 Chapter 8: PS/2 Mouse/Keyboard Port MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...

  • Page 71: Chapter 9: Digital To Analog Converter (Dac)

    (SPI_MOSI) to the selected bus slave—the DAC in this example. At the same time, the bus slave provides serial data (SPI_MISO) back to the bus master. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...

  • Page 72: Interface Signals

    FPGA communicates with the DAC to avoid bus contention. Table 9-2 provides the signals and logic values required to disable the other devices. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...

  • Page 73: Spi Communication Details

    As a new command enters the DAC, the previous 32-bit command word is echoed back to the MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...

  • Page 74: Specifying The Dac Output Voltage

    DAC outputs A and B. The reference voltage associated with DAC outputs A and B is 3.3V 5%. D 11:0 -------------------- - 3.3V Equation 9-2 OUTA 4096 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...

  • Page 75: Dac Outputs C And D

    LTC2624 Quad DAC Data Sheet http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1155,C1005,C1156, P2048,D2170 PicoBlaze Based D/A Converter Control for the Spartan-3E Starter Kit (Reference Design) http://www.xilinx.com/sp3e1600e Xilinx PicoBlaze Soft Processor http://www.xilinx.com/picoblaze Digilent, Inc. Peripheral Modules http://www.digilentinc.com/Products/Catalog.cfm?Nav1=Products& Nav2=Peripheral&Cat=Peripheral MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007...
  • Page 76 Chapter 9: Digital to Analog Converter (DAC) MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...

  • Page 77: Chapter 10: Analog Capture Circuit

    10-2). The output of pre-amplifier connects to a Linear Technology LTC1407A-1 ADC. Both the pre-amplifier and the ADC are serially programmed or controlled by the FPGA. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...

  • Page 78: Digital Outputs From Analog Inputs

    -2 and 2 -1. Therefore, the quantity is scaled by 8192, or 2 “Programmable Pre-Amplifier” to control the GAIN settings on the programmable pre-amplifier. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...

  • Page 79: Programmable Pre-Amplifier

    The gain of each amplifier is programmable from -1 to -100, as shown in Table 10-2. Table 10-2: Programmable Gain Settings for Pre-Amplifier Input Voltage Range Gain Minimum Maximum 1.025 2.275 1.525 1.775 1.5875 1.7125 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...

  • Page 80: Spi Control Interface

    All timing is minimum in nanoseconds unless otherwise noted. UG570_10_04_060706 Figure 10-4: SPI Timing When Communicating with Amplifier The amplifier interface is relatively slow, supporting only about a 10 MHz clock frequency. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...

  • Page 81: Ucf Location Constraints

    The maxim sample rate is approximately 1.5 MHz. The ADC presents the digital representation of the sampled analog values as a 14-bit, two’s complement binary value. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...

  • Page 82: Ucf Location Constraints

    Figure 10-7: Detailed SPI Timing to ADC UCF Location Constraints Figure 10-8 provides the User Constraint File (UCF) constraints for the amplifier interface, including the I/O pin assignment and I/O standard used. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...

  • Page 83: Disable Other Devices On The Spi Bus To Avoid Contention

    Connect AC signals to VINA or VINB via a DC blocking capacitor. Related Resources Amplifier and A/D Converter Control for the Spartan-3E Starter Kit (Reference Design) http://www.xilinx.com/sp3e1600e Xilinx PicoBlaze Soft Processor http://www.xilinx.com/picoblaze LTC6912 Dual Programmable Gain Amplifiers with Serial Digital Interface http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1154,C1009,C1121, P7596,D5359 LTC1407A-1 Serial 14-bit Simultaneous Sampling ADCs with Shutdown http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1155,C1001,C1158,...
  • Page 84 Chapter 10: Analog Capture Circuit MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...

  • Page 85: Chapter 11: Intel Strataflash Parallel Nor Flash Prom

    Stores two different FPGA configurations in the StrataFlash device and dynamically switch between the two using the Spartan-3E FPGA’s MultiBoot feature. Stores and executes MicroBlaze processor code directly from the StrataFlash device. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...

  • Page 86: Strataflash Connections

    StrataFlash device. Instead, the XC2C64 CPLD controls the pins during configuration. As described in Table 11-1 Shared Connections, some of the StrataFlash connections are shared with other components on the board. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...
  • Page 87 Connects to FPGA pins A[19:0] to support the BPI configuration. SF_A18 SF_A17 SF_A16 SF_A15 SF_A14 SF_A13 SF_A12 SF_A11 SF_A10 SF_A9 SF_A8 SF_A7 SF_A6 SF_A5 SF_A4 SF_A3 SF_A2 SF_A1 SF_A0 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...
  • Page 88 StrataFlash Byte Enable. Connects to FPGA pin LDC2 to support the BPI configuration. 0: x8 data 1: x16 data SF_STS StrataFlash Status signal. Connects to FPGA user-I/O pin. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...

  • Page 89: Shared Connections

    The FPGA accesses the StrataFlash PROM. Xilinx XC2C64A CPLD The Xilinx XC2C64A CoolRunner CPLD controls the five upper StrataFlash address lines, SF_A<24:20> during configuration. The four upper BPI-mode address lines from the FPGA, A<23:20> are not connected. Instead, four FPGA user-I/O pins connect to the StrataFlash PROM upper address lines SF_A<23:0>.

  • Page 90: Ucf Location Constraints

    LOC = "N10" | IOSTANDARD = LVCMOS33 | DRIVE = 6 | SLEW = SLOW ; UG257_11_03_060706 Figure 11-3: UCF Location Constraints for StrataFlash Data I/Os MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...

  • Page 91: Control

    A[24:20] during BPI configuration. Related Resources Intel J3 StrataFlash Data Sheet http://www.intel.com/design/flcomp/products/j3/techdocs.htm#datasheets ® Application Note 827, Intel StrataFlash Memory (J3) to Xilinx Spartan-3E FPGA Design Guide http://www.intel.com/design/flcomp/applnots/307257.htm MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...
  • Page 92 Chapter 11: Intel StrataFlash Parallel NOR Flash PROM MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...
  • Page 93 Serial data: Master Output, Slave Input SPI_MISO FPGA SPI Serial data: Master Input, Slave Output SPI_SCK FPGA SPI Clock SPI_SS_B FPGA SPI Asynchronous, active-Low slave select input MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...

  • Page 94: Chapter 12: Spi Serial Flash

    Set the FPGA configuration mode pins for SPI mode, as shown in Figure 12-4. The location of the configuration mode jumpers (J30) appears in Figure 12-3. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...

  • Page 95: Creating An Spi Serial Flash Prom File

    Regenerate the FPGA bitstream programming file with the new settings. UG257_12_05_060806 Figure 12-5: Set Configuration Rate to 12 MHz When Using the M25P16 SPI Flash MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...
  • Page 96 Formatter automatically swaps the bit direction as SPI Flash PROMs shift out the most- significant bit (MSB) first. Enter the Location of the directory and the PROM File Name. Click Next > when finished. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...
  • Page 97 The Spartan-3E Starter Kit board has a 16 Mbit SPI serial Flash PROM. Select 16M from the drop list, as shown in Figure 12-9. Click Next >. UG257_12_09_060806 Figure 12-9: Choose 16M MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...
  • Page 98 PROM, the select FPGA bitstream(s), and the amount of PROM space consumed by the bitstream. Figure 12-12 shows an example for a single XC1600E FPGA bitstream stored in an XCF04S Platform Flash PROM. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...
  • Page 99 The PROM Formatter creates an output file based on the settings shown in Figure 12-8. In this example, the output file is called MySPIFlash.mcs. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...

  • Page 100: Downloading The Design To Spi Flash

    Digilent JTAG3 programming cable These cables are not provided with the MicroBlaze Development Kit board , but can be purchased separately, either from the Xilinx Online Store or from Digilent, Inc. (see “Related Resources,” page 104). MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com...
  • Page 101 Force the FPGA’s PROG_B pin Low by installing a jumper on JP8, next to the PROG push button, as shown in Figure 12-16. See Figure 12-3, page 92 to locate jumper JP8 and surrounding landmarks. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...
  • Page 102 Finish : Mon Feb 27 13:38:22 2006 Elapsed clock time (00:01:15) = 75 seconds UG257_12_17_060806 Figure 12-17: Programming the M25P16 SPI Flash with the XSPI Programming Utility MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...

  • Page 103: Additional Design Details

    Table 12-3: Disable Other Devices on SPI Bus Signal Disabled Device Disable Value DAC_CS Digital-to-Analog Converter (DAC) AMP_CS Programmable Pre-Amplifier MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...

  • Page 104: Other Spi Flash Control Signals

    These pins must be left floating. Why support multiple packages? In a word, flexibility. The multi-package layout provides ... MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...
  • Page 105 Density migration between smaller- and larger-density SPI Flash PROMs. Not all SPI Flash densities are available in all packages. The SPI Flash migration strategy follows nicely with the pinout migration provided by Xilinx FPGAs. Consistent configuration PROM layout when migrating between FPGA densities.

  • Page 106: Related Resources

    Chapter 12: SPI Serial Flash Related Resources XAPP445: Configuring Spartan-3E Xilinx FPGAs with SPI Flash Memories http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?category= Application+Notes/FPGA+Features+and+Design/Configuration&show=xapp445.p XSPI SPI Flash Programming Utility http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?category= Application+Notes/FPGA+Features+and+Design/Configuration&show=xapp445.p Xilinx Parallel Cable IV with Flying Leads http://www.xilinx.com/xlnx/xebiz/productview.jsp?sGlobalNavPick=&category=- 19314 Digilent JTAG3 Programming Cable http://www.digilentinc.com/Products/Catalog.cfm?Nav1=Products&Nav2=Cables&C at=Cable STMicroelectronics M25P16 SPI Serial Flash Data Sheet http://www.st.com/stonline/books/pdf/docs/10027.pdf...

  • Page 107: Chapter 13: Ddr Sdram

    (K3) SD_CK_N (J4) SD_CK_P (B9) GCLK9 (J5) SD_CK_FB UG257_13_01_060806 Figure 13-1: FPGA Interface to Micron 512 Mbit DDR SDRAM All DDR SDRAM interface signals are terminated. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...

  • Page 108: Ddr Sdram Connections

    Table 13-1: FPGA-to-DDR SDRAM Connections DDR SDRAM FPGA Pin Category Signal Name Number Function SD_A12 Address inputs SD_A11 SD_A10 SD_A9 SD_A8 SD_A7 SD_A6 SD_A5 SD_A4 SD_A3 SD_A2 SD_A1 SD_A0 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...
  • Page 109 SD_LDM SD_UDQS Data Strobe. Upper and Lower data strobes SD_LDQS SD_CK_FB SDRAM clock feedback into top DCM within FPGA. Used by some DDR SDRAM controller cores MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...

  • Page 110: Ucf Location Constraints

    LOC = "L1" | IOSTANDARD = SSTL2_I ; NET "SD_DQ<0>" LOC = "L2" | IOSTANDARD = SSTL2_I ; UG257_13_03_060806 Figure 13-3: UCF Location Constraints for DDR SDRAM Data I/Os MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...

  • Page 111: Control

    CONFIG PROHIBIT = R4; UG257_13_05_060806 Figure 13-5: UCF Location Constraints for StrataFlash Control Pins Related Resources Xilinx Embedded Design Kit (EDK) http://www.xilinx.com/ise/embedded_design_prod/platform_studio.htm MT46V32M16 (32M x 16) DDR SDRAM Data Sheet http://download.micron.com/pdf/datasheets/dram/ddr/512MBDDRx4x8x16.pdf MicroBlaze OPB Double Data Rate (DDR) SDRAM Controller (v2.00b) http://www.xilinx.com/bvdocs/ipcenter/data_sheet/opb_ddr.pdf...
  • Page 112 Chapter 13: DDR SDRAM MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...
  • Page 113 25 MHz crystal oscillator. RJ-45 Ethernet Connector (J19) SMSC LAN83C185 10/100 Ethernet PHY Spartan-3E Development Board 25 MHz Crystal UG257_14_01_060806 Figure 14-1: 10/100 Ethernet PHY with RJ-45 Connector MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...

  • Page 114: Chapter 14: 10/100 Ethernet Physical Layer Interface

    Transmit Clock. 25 MHz in 100Base-TX mode, and 2.5 MHz in 10Base-T mode. E_RXD<4> Receive Data from PHY. E_RXD<3> E_RXD<2> E_RXD<1> E_RXD<0> E_RX_DV Receive Data Valid. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...

  • Page 115: Microblaze Ethernet Ip Cores

    Refer to the OPB Ethernet MAC data sheet (v1.02) for details. The OPB bus clock frequency must be 65 MHz or higher for 100 Mbps Ethernet operations and 6.5 MHz or faster for 10 Mbps Ethernet operations. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...

  • Page 116: Ucf Location Constraints

    Chapter 14: 10/100 Ethernet Physical Layer Interface The hardware evaluation versions of the Ethernet MAC cores operate for approximately eight hours in silicon before timing out. To order the full version of the core, visit the Xilinx website at: http://www.xilinx.com/ipcenter/processor_central/processor_ip/10-100emac/ 10-100emac_order_register.htm...

  • Page 117: Chapter 15: Expansion Connectors

    FX2_IP<38:35> and FX2_IP<40> are Input-only pins on the FPGA. These pins are highlighted in light green in Table 15-1 and cannot drive the FX2 connector but can receive signals. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...

  • Page 118: Voltage Supplies To The Connector

    Table 15-1 also highlights the shared connections to the eight discrete LEDs, the three 6-pin Accessory Headers (J1, J2, and J4), and the connectorless debugging header (J6). MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...
  • Page 119 FX2_IO2 FX2_IO3 FX2_IO4 FX2_IO5 FX2_IO6 FX2_IO7 FX2_IO8 FX2_IO9 FX2_IO10 FX2_IO11 FX2_IO12 FX2_IO13 FX2_IO14 FX2_IO15 FX2_IO16 FX2_IO17 FX2_IO18 FX2_IO19 FX2_IO20 FX2_IO21 FX2_IO22 FX2_IO23 FX2_IO24 FX2_IO25 FX2_IO26 FX2_IO27 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...

  • Page 120: Compatible Board

    LVDS or RSDS I/O standards, as listed in Table 15-2. All I/O pairs support differential input termination (DIFF_TERM) as described in the MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...
  • Page 121 IO_L08P_0 FX2_IO19 IO_L06N_0 R203 FX2_IO20 IO_L06P_0 FX2_IO21 IO_L05P_0 R204 FX2_IO22 IO_L05N_0 FX2_IO23 IO_L04N_0 R205 FX2_IO24 IO_L04P_0 FX2_IO25 IO_L03N_0 R206 FX2_IO26 IO_L03P_0 FX2_IO27 IO_L01N_0 R207 FX2_IO28 IO_L01P_0 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...
  • Page 122 Table 15-2 indicates which resistor is associated with a specific differential pair. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...
  • Page 123 If using differential outputs on the FX2 connector, set jumper JP9 to 2.5V. If the jumper is not set correctly, the outputs switch correctly but the signal levels are out of specification. FPGA LxxN_0 Signal LxxP_0 UG257_15_06_060806 Figure 15-6: Differential Outputs MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...

  • Page 124: Ucf Location Constraints

    #NET "FX2_IP<40>" LOC = "C15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; UG257_15_07_062106 Figure 15-7: UCF Location Constraints for Accessory Headers MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...

  • Page 125: Six-Pin Accessory Headers

    J2<4:1>. The board supplies 3.3V to the accessory board mounted in the J4 socket on the bottom pin. Spartan-3E FPGA J2<0> (P12) J2<1> (N12) J2<2> (V6) J2<3> (V5) 3.3V UG257_15_09_082907 Figure 15-9: FPGA Connections to the J2 Accessory Header MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...

  • Page 126: Header J4

    #NET "J4<3>" LOC = "E8" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ; UG257_15_11_062106 Figure 15-11: UCF Location Constraints for Accessory Headers MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...

  • Page 127: Connectorless Debugging Port Landing Pads (J6)

    Agilent, provides an interface to a logic analyzer. This debugging port is intended primarily for the Xilinx ChipScope Pro software with the Agilent’s FPGA Dynamic Probe. It can, however, be used with either the Agilent or Tektronix probes, without the ChipScope software, using FPGA Editor’s probe command.

  • Page 128: Related Resources

    Hirose connectors http://www.hirose-connectors.com/ FX2 Series Connector Data Sheet http://www.hirose.co.jp/cataloge_hp/e57220088.pdf Digilent, Inc. Peripheral Modules http://www.digilentinc.com/Products/Catalog.cfm?Nav1=Products&Nav2=Peripheral&Cat=Peripheral Xilinx ChipScope Pro Tool http://www.xilinx.com/ise/optional_prod/cspro.htm Agilent B4655A FPGA Dynamic Probe for Logic Analyzer http://www.home.agilent.com/USeng/nav/-536898189.536883660/pd.html?cmpid=92641 Agilent 5404A/6A Pro Series Soft Touch Connector http://www.home.agilent.com/cgi-bin/pub/agilent/Product/cp_Product.jsp?NAV_ID=-536898227.0.00 Tektronix P69xx Probe Module s with D-Max Technology http://www.tek.com/products/accessories/logic_analyzers/p6800_p6900.html...

  • Page 129: Chapter 16: Xc2C64A Coolrunner-Ii Cpld

    The CPLD is user programmable and available for customer applications. Portions of the CPLD are reserved to coordinate behavior between the various FPGA configuration memories, namely the Xilinx Platform Flash PROM and the Intel StrataFlash PROM. Consequently, the CPLD must provide the following functions in addition to the user application.

  • Page 130: Ucf Location Constraints

    Figure 16-1: XC2C64A CoolRunner-II CPLD Controls Master Serial and BPI Configuration Modes UCF Location Constraints – There are two sets of constraints listed below one for the Spartan-3E FPGA and one for the XC2C64A CoolRunner-II CPLD. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...

  • Page 131: Fpga Connections To Cpld

    LOC = "P20" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ; NET "SF_A<20>" LOC = "P19" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ; UG257_16_03_060806 Figure 16-3: UCF Location Constraints for the XC2C64A CPLD MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...

  • Page 132: Related Resources

    Chapter 16: XC2C64A CoolRunner-II CPLD Related Resources CoolRunner-II CPLD Family Data Sheet http://direct.xilinx.com/bvdocs/publications/ds090.pdf XC2C64A CoolRunner-II CPLD Data Sheet http://direct.xilinx.com/bvdocs/publications/ds311.pdf Default XC2C64A CPLD Design for Spartan-3E Starter Kit Board http://www.xilinx.com/s3estarter MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...

  • Page 133: Ucf Location Constraints

    1-Wire interface, which uses a single wire for power and serial communication. The DS2432 EEPROM offers one of many possible means to copy and protect the FPGA configuration bitstream, thereby making cloning difficult. Xilinx application note XAPP780, listed under “Related Resources”...
  • Page 134 Chapter 17: DS2432 1-Wire SHA-1 EEPROM MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...
  • Page 135 “Intel StrataFlash Parallel NOR Flash Memory and Micron DDR SDRAM ” “Buttons, Switches, Rotary Encoder, and Character LCD ” “DDR SDRAM Series Termination and FX2 Connector Differential Termination” MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...

  • Page 136: Fx2 Expansion Header, 6-Pin Headers, And Connectorless Probe Header

    Header J7 provides the two analog inputs to the programmable pre-amplifier (AMP) and two-channel Analog-to-Digital Converter (ADC). The diagram in the lower left corner shows the JTAG chain. Chapter 15, “Expansion Connectors,” for additional information. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...
  • Page 137 FX2 Expansion Header, 6-pin Headers, and Connectorless Probe Header UG257_A01_060606 Figure 18-1: Schematic Sheet 1 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...

  • Page 138: Rs-232 Ports, Vga Port, And Ps/2 Port

    The SMA connector allows an external clock source to drive one of the FPGA’s global clock inputs. Alternatively, the FPGA can provide a high-performance clock to another board via the SMA connector. See Chapter 3, “Clock Sources,” for additional information. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...
  • Page 139 RS-232 Ports, VGA Port, and PS/2 Port UG257_A02_060606 Figure 18-2: Schematic Sheet 2 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...

  • Page 140: Ethernet Phy, Magnetics, And Rj-11 Connector

    Ethernet MAC implemented within the FPGA. J19 is the RJ-11 Ethernet connector associated with the 10/100 Ethernet PHY. Chapter 14, “10/100 Ethernet Physical Layer Interface,” for additional information. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...
  • Page 141 Ethernet PHY, Magnetics, and RJ-11 Connector UG257_A03_060606 Figure 18-3: Schematic Sheet 4 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...

  • Page 142: Voltage Regulators

    Resistors R65 and R67 create a voltage divider to create the termination voltage required for the DDR SDRAM interface. IC9 is a 1.8V supply to the Embedded USB download/debug circuit and to the CPLD’s VCCINT supply input. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...
  • Page 143 Voltage Regulators UG257_A04_060606 Figure 18-4: Schematic Sheet 5 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...

  • Page 144: Fpga Configurations Settings, Platform Flash Prom, Spi Serial Flash, Jtag

    IC14 and IC15 are alternate landing pads for the STMicro SPI serial Flash. IC14 accepts the 16-pin SOIC package option, while IC15 accepts either the 8-pin SOIC or MLP package option. See Figure 12-19, page 103 for additional informaton. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...
  • Page 145 FPGA Configurations Settings, Platform Flash PROM, SPI Serial Flash, JTAG Connections UG257_A05_060606 Figure 18-5: Schematic Sheet 6 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...

  • Page 146: Fpga I/O Banks 0 And 1, Oscillators

    IC17 is the 50 MHz clock oscillator. Chapter 3, “Clock Sources,” for additional information. IC16 is an 8-pin DIP socket to insert an alternate clock oscillator with a different frequency. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...
  • Page 147 FPGA I/O Banks 0 and 1, Oscillators UG257_A06_060606 Figure 18-6: Schematic Sheet 7 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...

  • Page 148: Fpga I/O Banks 2 And 3" "Power Supply Decoupling

    IC10B3 represents the connections to I/O Bank 3 on the FPGA. Bank 3 is dedicated to the DDR SDRAM interface and is consequently powered by 2.5V. See Chapter 13, “DDR SDRAM,” for additional information. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...
  • Page 149 FPGA I/O Banks 2 and 3 UG257_A07_060606 Figure 18-7: Schematic Sheet 8 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...
  • Page 150 Jumper JP9 defines the voltage applied to VCCO on I/O Bank 0. The default setting is 3.3V. “Voltage Control,” page 20 “Voltage Supplies to the Connector,” page 116 additional details. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...
  • Page 151 Power Supply Decoupling UG257_A08_060606 Figure 18-8: Schematic Sheet 9 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...

  • Page 152: Xc2C64A Coolrunner-Ii Cpld

    Appendix A: Schematics XC2C64A CoolRunner-II CPLD IC18 is a Xilinx XC2C64A CoolRunner-II CPLD. The CPLD primarily provides additional flexibility when configuring the FPGA from parallel NOR Flash and during MultiBoot configurations. When the CPLD is loaded with the appropriate design, JP10 enables a watchdog timer in the CPLD used during fail-safe MultiBoot configurations.
  • Page 153 XC2C64A CoolRunner-II CPLD UG257_A09_060606 Figure 18-9: Schematic Sheet 10 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...

  • Page 154: Linear Technology Adc And Dac

    Chapter 10, “Analog Capture Circuit,” for additional information. IC21 is a Linear Technology LTC2624 four-channel DAC. See Chapter 9, “Digital to Analog Converter (DAC),” for additional information. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...
  • Page 155 Linear Technology ADC and DAC UG257_A10_060606 Figure 18-10: Schematic Sheet 11 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...

  • Page 156: Intel Strataflash Parallel Nor Flash Memory And Micron Ddr Sdram

    “Intel StrataFlash Parallel NOR Flash PROM,” for additional information. IC23 is a 512 Mbit (64 Mbyte) Micron DDR SDRAM. See Chapter 13, “DDR SDRAM,” additional information. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...
  • Page 157 Intel StrataFlash Parallel NOR Flash Memory and Micron DDR SDRAM UG257_A11_060606 Figure 18-11: Schematic Sheet 12 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...

  • Page 158: Buttons, Switches, Rotary Encoder, And Character Lcd

    LD0 through LD7 are discrete LEDs. Chapter 2, “Switches, Buttons, and Knob,” for additional information. DISP1 is a 2x16 character LCD screen. See Chapter 5, “Character LCD Screen,” additional information. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...
  • Page 159 Buttons, Switches, Rotary Encoder, and Character LCD UG257_A12_060606 Figure 18-12: Schematic Sheet 13 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...

  • Page 160: Ddr Sdram Series Termination And Fx2 Connector Differential Termination

    Resistors R202 through R210 are not loaded on the board. These landing pads provide optional connections for 100 differential termination resistors. See “Using Differential Inputs,” page 120 for additional information. MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...
  • Page 161 DDR SDRAM Series Termination and FX2 Connector Differential Termination UG257_A13_060606 Figure 18-13: Schematic Sheet 14 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...
  • Page 162 Appendix A: Schematics MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...
  • Page 163 NET "SW<2>" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ; NET "SW<3>" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP ; # ==== Discrete LEDs (LED) ==== MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...
  • Page 164 NET "E_RXD<1>" LOC = "T11" | IOSTANDARD = LVCMOS33 ; NET "E_RXD<2>" LOC = "U11" | IOSTANDARD = LVCMOS33 ; NET "E_RXD<3>" LOC = "V14" | IOSTANDARD = LVCMOS33 ; MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...
  • Page 165 NET "SD_CK_FB" LOC = "B9" | IOSTANDARD = LVCMOS33 ; # Prohibit VREF pins CONFIG PROHIBIT = D2; CONFIG PROHIBIT = G4; CONFIG PROHIBIT = J6; CONFIG PROHIBIT = L5; MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...
  • Page 166 NET "VGA_HSYNC" LOC = "F15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; NET "VGA_RED" LOC = "H14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide www.xilinx.com UG257 (v1.1) December 5, 2007...
  • Page 167 #NET "J2<2>" LOC = "V6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ; #NET "J2<3>" LOC = "V5" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ; MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 www.xilinx.com...
  • Page 168 #NET "INPUT_IO<14>" LOC = "P15" | PULLDOWN | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = # ==== Xilinx CPLD (XC) ==== NET "XC_CMD<0>" LOC = "P18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;...

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