Xilinx SelectIO 7 Series User Manual page 3

Date Version
07/20/2012 1.2
(Cont'd)
10/31/2012 1.3
05/13/2014 1.4
UG471 (v1.10) May 8, 2018
Updated ILOGIC Resources. In
T . Updated Input Delay Resources
ICE1Q
LD port in Table 2-4. In IDELAY
Increment/Decrement Signals - CE,
LDPIPEEN and Pipeline Register Reset -
Descriptions." Updated descriptions of IDELAY_TYPE and IDELAY_VALUE in
Table 2-5. Updated IDELAY_TYPE
HIGH_PERFORMANCE_MODE
before Figure 2-12. Updated
Updated IDELAYCTRL, including
OLOGICE3 to OLOGIC Resources. Updated first paragraph of
(ODELAY)—Not Available in HR
CNTVALUEIN, LDPIPEEN, and CNTVALUEOUT in
VAR_LOAD_PIPE mode to
LDPIPEEN and Pipeline Register Reset -
CNTVALUEIN, Count Value Out -
Signals - CE, INC. Removed Table 2-14: "Control Pin Descriptions." Updated
descriptions of ODELAY_TYPE and ODELAY_VALUE in
Attributes. Added ODELAY
Updated Reset Input - RST, page
Table 3-2. Updated bulleted list after
Updated Figure 3-7. Updated
Data Parallel-to-Serial Converter. Deleted the OCBEXTEND pin in
descriptions of OFB and TFB in
- OFB, 3-state Control Output -
OSERDESE2 Clocking Methods
in Table 3-11. Added IO_FIFO
Added Appendix A, Termination Options for SSO Noise
Removed XC7V1500T from third bullet after
Updated V . Added item to bulleted list after
CCO
Figure 1-10. In VRN/VRP External Resistance Design Migration
first two paragraphs and added description of power rating. Updated title of
and Figure 1-12. Updated
Figure 1-14. Updated first paragraph of
I/O Banks (IN_TERM). Added IOBUF_DCIEN, IOBUF_INTERMDISABLE,
IOBUFDS_DIFF_OUT_DCIEN, IOBUFDS_DIFF_OUT_INTERMDISABLE, and
IOBUFDS_INTERMDISABLE to
from Figure 1-22 and following description. Updated
II_T_DCI_18. Added IBUFDS_DIFF_OUT_INTERMDISABLE, IOBUF_DCIEN, and
IOBUF_INTERMDISABLE. Updated connections in
Figure 1-31, and Figure 1-32. Reversed R
Figure 1-49, Figure 1-50, Figure
Figure 1-58, Figure 1-60, Figure
SSTL135, DIFF_SSTL18_II, DIFF_SSTL15,
SSTL (Stub-Series Terminated
description of source termination series resistors from
DIFF_SSTL18_I_DCI, SSTL18_II, SSTL15, SSTL135, DIFF_SSTL18_II, DIFF_SSTL15,
DIFF_SSTL135, SSTL18_II_DCI, SSTL_15_DCI, SSTL135_DCI, DIFF_SSTL18_II_DCI,
DIFF_SSTL_15_DCI, DIFF_
SSTL135_T_DCI, DIFF_SSTL18_II_T_DCI, DIFF_SSTL15_T_DCI, DIFF_
SSTL135_T_DCI, and SSTL12, SSTL12_DCI, SSTL12_T_DCI, DIFF_SSTL12,
DIFF_SSTL12_DCI, DIFF_SSTL12_T_DCI. Updated
www.xilinx.com
Revision
Table 2-3, added T
ICOCKD
(IDELAY). Updated functional description of
Ports, updated Module Load - LD
INC, and added
REGRST. Removed Table 2-5: "Control Pin
Attribute, IDELAY_VALUE
Attribute. Updated
Stability after an Increment/Decrement
Figure 2-16. Added paragraph about OLOGICE2 and
Banks. Updated functions of REGRST, LD,
Module Load - LD. Added
REGRST. Updated
CNTVALUEOUT, and
Modes. Updated text before
149. Added INIT_Q and SRVAL_Q attributes to
Figure 3-6 and in
ISERDESE2 Width Expansion,
Table 3-6. Updated Output Feedback from OSERDESE2
TFB, and Reset Input - RST, page
and OSERDESE2 Width
Overview. Updated Resetting the
Figure 1-7.
Figure
step 4 of DCI in 7 Series FPGAs I/O
Uncalibrated Split Termination in High-Range
7 Series FPGA SelectIO
and R
VRN VRP
1-52, Figure 1-54, Figure
1-62, and Figure 1-63. Added note to
DIFF_SSTL135. Updated fifth paragraph of
Logic). Removed Thevenin equivalent of R/2 and
SSTL135_DCI, SSTL18_II_T_DCI, SSTL15_T_DCI,
Figure 1-57
7 Series FPGAs SelectIO Resources User Guide
/T and removed
IOCKDD
and
Pipeline Register Load -
Attribute, and
IDELAY Timing. Updated text
Operation.
Output Delay Resources
Table 2-13. Added description of
Pipeline Register Load -
Count Value In -
Increment/Decrement
Table 2-14. Updated ODELAY
Figure 2-26.
MEMORY Interface Type.
BITSLIP Submodule, and
Figure 3-14. Updated
164. Updated
Expansion. Updated latencies
IO_FIFO.
Analysis.
1-7. Updated paragraph after
Guidelines, updated
Figure 1-11
Standards. Updated
Primitives. Removed O output
HSTL_ II_T_DCI and HSTL_
Figure 1-28, Figure 1-30,
in Figure 1-46, Figure 1-48,
1-55, Figure 1-56, Figure
SSTL18_II, SSTL15,
SSTL18_I_DCI,
and Figure 1-59.
1-57,