Xilinx SelectIO 7 Series User Manual
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Xilinx SelectIO 7 Series User Manual

Xilinx SelectIO 7 Series User Manual

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7 Series FPGAs
SelectIO Resources
User Guide
UG471 (v1.10) May 8, 2018

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Summary of Contents for Xilinx SelectIO 7 Series

  • Page 1 7 Series FPGAs SelectIO Resources User Guide UG471 (v1.10) May 8, 2018...

  • Page 2: Revision History

    Limited Warranties which can be viewed at http://www.xilinx.com/warranty.htm; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance;...
  • Page 3 DIFF_SSTL135, SSTL18_II_DCI, SSTL_15_DCI, SSTL135_DCI, DIFF_SSTL18_II_DCI, DIFF_SSTL_15_DCI, DIFF_ SSTL135_DCI, SSTL18_II_T_DCI, SSTL15_T_DCI, SSTL135_T_DCI, DIFF_SSTL18_II_T_DCI, DIFF_SSTL15_T_DCI, DIFF_ SSTL135_T_DCI, and SSTL12, SSTL12_DCI, SSTL12_T_DCI, DIFF_SSTL12, DIFF_SSTL12_DCI, DIFF_SSTL12_T_DCI. Updated Figure 1-57 Figure 1-59. UG471 (v1.10) May 8, 2018 www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide...
  • Page 4 3-6. Updated input span to D1–D8 in Timing Characteristics of 8:1 DDR Serialization. 05/08/2018 1.10 Expanded descriptions in Parallel 3-state Inputs - T1 to T4 DATA_RATE_TQ Attribute. Added note after Table 3-11. 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com UG471 (v1.10) May 8, 2018...

  • Page 5: Table Of Contents

    Xilinx DCI ........
  • Page 6 ......77 DIFF_SSTL15_T_DCI, DIFF_ SSTL135_T_DCI SSTL12, SSTL12_DCI, SSTL12_T_DCI, DIFF_SSTL12, DIFF_SSTL12_DCI, DIFF_SSTL12_T_DCI www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback...
  • Page 7 ............126 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback...
  • Page 8 Dynamic Clock Inversions ..........156 www.xilinx.com...
  • Page 9 ALMOST EMPTY and ALMOST FULL Flags ....... . 180 Appendix A: Termination Options for SSO Noise Analysis 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...
  • Page 10 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 11: Preface: About This Guide

    Preface About This Guide Xilinx® 7 series FPGAs include four FPGA families that are all designed for lowest power to enable a common design to scale across families for optimal power, performance, and cost. The Spartan®-7 family is the lowest density with the lowest cost entry point into the 7 series portfolio.
  • Page 12 Preface: About This Guide www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 13: Chapter 1: Selectio Resources

    24 mA drive option for LVCMOS18 and LVTTL outputs Supported supply rail Supported CCAUX_IO Digitally-controlled impedance (DCI) and DCI cascading Supported Internal V Supported Supported 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 14: New Features

    Thevenin-equivalent resistance, whereas in Virtex-6 FPGAs and earlier families they were chosen to be equal to the target Thevenin-equivalent resistance. See the Xilinx DCI section for more details. • There are additional I/O Logic design primitives with new features and functions. See Chapter 2, SelectIO Logic Resources for more details on these primitives.

  • Page 15: Selectio Resources Introduction

    ISERDES and OSERDES, respectively, as described in Chapter 3, Advanced SelectIO Logic Resources. X-Ref Target - Figure 1-1 PADOUT DCITERMDISABLE DIFFI_IN IBUFDISABLE UG471_c1_03_010711 Figure 1-1: Single-Ended (Only) HP IOB Diagram 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...
  • Page 16 UG471_c1_05 _011010 Figure 1-3: Single-Ended (Only) HR IOB Diagram X-Ref Target - Figure 1-4 PADOUT DIFFI_IN DIFFO_OUT IBUFDISABLE O_OUT UG471_c1_06_011110 Figure 1-4: Regular HR IOB Diagram www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 17: Selectio Resources General Guidelines

    Bank 13 Bank 33 50 I/0 50 I/0 Bank 12 Bank 32 50 I/0 50 I/0 UG471_c1_07_032111 Figure 1-5: 7 Series FPGA XC7K325T I/O Banks 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 18: Supply Voltages For The Selectio Pins

    I/Os. The 2.0V option is available when the slightly-increased performance is required for the very fastest bit rates supported for the single-ended drivers. www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback...

  • Page 19: State Of I/Os During And After Configuration

    I/Os, adding resistors close to the device pins increases the board area and component count, and can in some cases be physically impossible. To address these issues and to achieve better signal integrity, Xilinx developed the digitally controlled impedance (DCI) technology.

  • Page 20: Xilinx Dci

    DCI is only available in 7 series FPGAs HP I/O banks. DCI is not available in HR I/O banks. Xilinx DCI DCI uses two multi-purpose reference pins in each I/O bank to control the impedance of the driver or the parallel-termination value for all of the I/Os of that bank.

  • Page 21: Match_Cycle Configuration Option

    DCIUpdateMode is a configuration option that can override control of how often the DCI circuit updates the impedance matching to the VRN and VRP reference resistors. This option defaults to AsRequired but also has an optional value of Quiet in the Xilinx implementation software. The settings for the DCIUpdateMode configuration option are: •...

  • Page 22: Dcireset Primitive

    Chapter 1: SelectIO Resources DCIRESET Primitive DCIRESET is a Xilinx design primitive that provides the capability to perform a reset of the DCI controller state machine during normal operation of the design. Unless DCIUpdateMode is set to Quiet (see DCIUpdateMode Configuration...
  • Page 23 Bank VRN/VRP Bank B Local Bank Bank C Local Bank To Banks Below (When Cascaded) UG471_c1_09_011811 Figure 1-7: DCI Cascading Supported Over Multiple I/O Banks 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...
  • Page 24 For specific information on implementing DC cascading in a design, see DCI_CASCADE Constraint, page • Xilinx recommends that unused banks be powered up because leaving the V pins of unused I/O banks floating reduces the level of ESD protection on these pins and the I/O pins in the bank.

  • Page 25: Controlled Impedance Driver (Source Termination)

    Z X-Ref Target - Figure 1-9 7 Series FPGA HP Bank DCI UG471_c1_11_101810 Figure 1-9: Controlled Impedance Driver with Half Impedance 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 26: Split-Termination Dci (Thevenin Equivalent Termination To Vcco/2)

    DIFF_HSTL_I_DCI_18 SSTL18_II_DCI DIFF_SSTL18_II_DCI HSTL_II_DCI DIFF_HSTL_II_DCI SSTL18_II_T_DCI DIFF_SSTL18_II_T_DCI HSTL_II_DCI_18 DIFF_HSTL_II_DCI_18 SSTL15_DCI DIFF_SSTL15_DCI HSTL_II_T_DCI DIFF_HSTL_II_T_DCI SSTL15_T_DCI DIFF_SSTL15_T_DCI HSTL_II_T_DCI_18 DIFF_HSTL_II_T_DCI_18 SSTL135_DCI DIFF_SSTL135_DCI SSTL135_T_DCI DIFF_SSTL135_T_DCI SSTL12_DCI DIFF_SSTL12_DCI SSTL12_T_DCI DIFF_SSTL12_T_DCI www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 27: Vrn/Vrp External Resistance Design Migration Guidelines

    (External Resistors on VRN, VRP = 2R) VRN/VRP External Resistance Design Migration Guidelines Previous Xilinx FPGA families featuring DCI used a slightly different circuit for calibrating the split-termination impedance from the external reference resistors placed on the VRN and VRP pins. The Virtex-6 FPGA DCI calibrates each leg of the split-termination circuit to be double the external resistor values.

  • Page 28: Dci And 3-State Dci (T_Dci)

    The T_DCI standards can only be assigned to bidirectional pins. For unidirectional input pins, the DCI version of the standard can be assigned. For unidirectional output pins, either the non-DCI or the DCI version can be assigned. www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback...

  • Page 29: Dci In 7 Series Fpgas I/O Standards

    SSTL18_II_T_DCI DIFF_SSTL18_II_T_DCI LVDCI_DV2_15 HSTL_II_DCI_18 DIFF_HSTL_II_DCI_18 SSTL15_DCI DIFF_SSTL15_DCI HSLVDCI_18 HSTL_II_T_DCI DIFF_HSTL_II_T_DCI SSTL15_T_DCI DIFF_SSTL15_T_DCI HSLVDCI_15 HSTL_II_T_DCI_18 DIFF_HSTL_II_T_DCI_18 SSTL135_DCI DIFF_SSTL135_DCI SSTL135_T_DCI DIFF_SSTL135_T_DCI SSTL12_DCI DIFF_SSTL12_DCI SSTL12_T_DCI DIFF_SSTL12_T_DCI HSUL_12_DCI DIFF_HSUL_12_DCI 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...
  • Page 30 50Ω Thevenin equivalent termination (R) to V /2, the external reference resistors should each be 100Ω, which is (2R). Xilinx requires that the exact same value of the resistance be used on the VRP and VRN pins in order to achieve the expected DCI behavior.

  • Page 31: Dci Usage Examples

    VRN = VRP = 2R = 2Z 0 Resistor 50Ω 50Ω Recommended Notes: 1. Z 0 is the recommended PCB trace impedance. UG471_c1_15_011811 Figure 1-13: HSTL DCI Usage Examples 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...
  • Page 32 VRN = VRP = 2R = 2Z 0 Resistor 50Ω 50Ω Recommended Notes: 1. Z 0 is the recommended PCB trace impedance. ug471_c1_16_042413 Figure 1-14: SSTL DCI Usage Examples www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...
  • Page 33 Table 1-7: I/O Standards that Support IN_TERM HSTL_I DIFF_HSTL_I SSTL15_R DIFF_SSTL15_R DIFF_HSTL_II SSTL15 DIFF_SSTL15 HSTL_II HSTL_I_18 DIFF_HSTL_I_18 SSTL135_R DIFF_SSTL135_R HSTL_II_18 DIFF_HSTL_II_18 SSTL135 DIFF_SSTL135 SSTL18_ DIFF_SSTL18_I SSTL18_II DIFF_SSTL18_II 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 34: Series Fpga Selectio Primitives

    SelectIO Resources 7 Series FPGA SelectIO Primitives The Xilinx software library includes an extensive list of primitives to support a variety of I/O standards available in the 7 series FPGA I/O primitives. The following generic primitives can each support most of the available single-ended I/O standards.

  • Page 35: Ibuf And Ibufg

    Figure 1-15: Input Buffer Primitives (IBUF/IBUFG) The IBUF and IBUFG primitives are the same. IBUFGs are used when an input buffer is used as a clock input. In the Xilinx software tools, an IBUFG is automatically placed at clock input sites.

  • Page 36: Ibuf_Intermdisable

    X-Ref Target - Figure 1-18 IBUFDS/IBUFGDS Output to FPGA – Inputs from device pads ug471_c1_21_041112 Figure 1-18: Differential Input Buffer Primitives (IBUFDS/IBUFGDS) www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 37: Ibufds_Diff_Out And Ibufgds_Diff_Out

    (O and OB). IBUFDS_DIFF_OUT and IBUFGDS_DIFF_OUT primitives are the same, IBUFGDS_DIFF_OUT is used for clock inputs. These primitives are only recommended for use by experienced Xilinx designers. X-Ref Target - Figure 1-19 IBUFDS_DIFF_OUT/IBUFGDS_DIFF_OUT...

  • Page 38: Ibufds_Intermdisable

    The IBUFDS_DIFF_OUT_ INTERMDISABLE primitive shown in Figure 1-23 is available in the HR I/O banks and is similar to the IBUFDS_IBUFDISABLE primitive in that it has an www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 39: Iobuf

    The IOBUF_DCIEN primitive also has a DCITERMDISABLE port that can be used to manually disable the optional DCI split-termination feature. See 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 40: Iobuf_Intermdisable

    X-Ref Target - Figure 1-26 IOBUF_INTERMDISABLE IBUFDISABLE INTERMDISABLE UG471_c1_75_021414 Figure 1-26: Bidirectional Buffer With Input Path Disable and IN_TERM Disable (IOBUF_INTERMDISABLE) www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 41: Iobufds

    DCITERMDISABLE port that can be used to manually disable the optional DCI split-termination feature. See Split-Termination DCI (Thevenin Equivalent Termination to VCCO/2) DCI and 3-state DCI (T_DCI) for more details. 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 42: Iobufds_Diff_Out

    Figure 1-29 shows the differential input/output buffer primitive with complementary outputs (O and OB). This primitive is only recommended for use by experienced Xilinx designers with memory interface applications. A logic High on the T pin disables the output buffer.

  • Page 43: Iobufds_Diff_Out_Dcien

    TRUE and the IBUFDISABLE signal is asserted High. If USE_IBUFDISABLE is set to FALSE, this input is ignored and should be tied to ground. If the I/O is using the 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 44: Iobufds_Diff_Out_Intermdisable

    I/O banks. It has an IBUFDISABLE port that can be used to disable the input buffer during periods that the buffer is not being used. The IOBUFDS_INTERMDISABLE primitive also has an INTERMDISABLE port that can be used to disable the optional uncalibrated www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback...

  • Page 45: Obuf

    I (Input) O (Output) From FPGA to device pad ug471_c1_18_011811 Figure 1-33: Output Buffer Primitive (OBUF) OBUFDS Figure 1-34 shows the differential output buffer primitive. 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 46: Obuft

    UG912: Vivado Design Suite Properties Reference Guide. DCI_CASCADE Constraint The DCI_CASCADE constraint identifies a DCI master bank and its corresponding slave banks. See DCI Cascading, page 22 for more information. www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 47: Location Constraints

    LVDS • LVDS_25 • PPDS_25 • RSDS_25 • MINI_LVDS_25 • BLVDS_25 • DIFF_HSTL (all variations) • DIFF_SSTL (all variations) • DIFF_MOBILE_DDR • DIFF_HSUL (all variations) 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 48: Output Slew Rate Attributes

    2, 4, 6, 8, 12, or 16 LVCMOS25 4, 8, 12, or 16 LVCMOS33 4, 8, 12, or 16 LVTTL 4, 8, 12, 16, or 24 www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 49: Pullup/Pulldown/Keeper Attribute For Ibuf, Obuft, And Iobuf

    Refer to the ISE tools language templates or the 7 series FPGA HDL Libraries Guide for the proper syntax for instantiating these primitives and setting the DIFF_TERM attribute. The allowed values for the DIFF_TERM attribute are: • DIFF_TERM = TRUE 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 50: Internal Vref

    1.8V, at least one I/O net or primitive in that CCAUX_IO bank should have this constraint set to NORMAL, and all other I/O nets or primitives should be set to either NORMAL or DONTCARE. www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 51: Series Fpga I/O Resource Vhdl/Verilog Examples

    7 Series FPGA I/O Resource VHDL/Verilog Examples The VHDL and Verilog example syntaxes for instantiating 7 series FPGA I/O resources are found in UG768: Xilinx 7 Series FPGA Libraries Guide for HDL Designs. Supported I/O Standards and Terminations The following sections provide an overview of the I/O standards and options supported by all 7 series devices.
  • Page 52 R S = Z 0 – R D LVTTL LVTTL R P = Z 0 Note: V is any voltage from 0V to V CCO ug471_c1_27_011811 Figure 1-37: LVTTL Unidirectional Termination www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...
  • Page 53 Table 1-10: Allowed Attributes for the LVTTL I/O Standards Primitives Attributes IBUF/IBUFG OBUF/OBUFT/ IOBUF IOSTANDARD LVTTL LVTTL DRIVE 4, 8, 12 (default), 16, 24 SLEW {FAST, SLOW} 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 54: Lvcmos (Low Voltage Cmos)

    R S = Z 0 – R D LVCMOS LVCMOS R P = Z 0 Note: V is any voltage from 0V to V CCO ug471_c1_29_011811 Figure 1-39: LVCMOS Unidirectional Termination www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...
  • Page 55 HP I/O Banks HR I/O Banks IOSTANDARD LVCMOS18 LVCMOS18 LVCMOS18 DRIVE 2, 4, 6, 8, 12, 16 4, 8, 12, 16, 24 SLEW {FAST, SLOW} {FAST, SLOW} 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 56: Lvdci (Low-Voltage Digitally Controlled Impedance)

    Sample circuits illustrating both unidirectional and bidirectional topologies for a controlled impedance driver are shown in Figure 1-41 Figure 1-42. The DCI I/O standards supporting a controlled impedance driver are: LVDCI_15 and LVDCI_18. www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 57: Lvdci_Dv2

    To match the drive impedance to Z when using a driver with half impedance, the reference resistor R must be twice Z 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...
  • Page 58 There are no optional current drive strength settings for LVDCI drivers. When the driver impedance is one-half of the VRN/VRP reference resistors, it is indicated by the addition of DV2 to the attribute name. www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback...

  • Page 59: Hslvdci (High-Speed Lvdci)

    Figure 1-45: HSLVDCI Controlled Impedance Driver with Bidirectional Termination For electrical specifications, refer to the LVDCI V and V entries in the 7 series data sheets. 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 60: Hstl (High-Speed Transceiver Logic)

    Table 1-22: Available I/O Bank Type Available Available HSTL_II and HSTL_II_18 use V /2 as a parallel-termination voltage (V ) and are intended for use in bidirectional links. www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 61: Hstl_ Ii_Dci And Hstl_ Ii_Dci_18

    Available Differential HSTL class-II pairs complementary single-ended HSTL_II type drivers with a differential receiver. Differential HSTL class-II is intended to be used in bidirectional links. 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 62: Diff_Hstl_Ii_Dci And Diff_Hstl_Ii_Dci_18

    1.2V, 1.5V, or 1.8V versions. In a specific circuit, all drivers and receivers must be at the same voltage level (either 1.2V, 1.5V or 1.8V); they are not interchangeable. Only HP I/O banks support the DCI standards. www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback...
  • Page 63 HSTL_I_DCI_18 = 0.75V for HSTL_I_DCI – 0.9V for HSTL_I_DCI_18 = 2Z 0 = 100Ω ug471_c1_36_021214 Figure 1-46: HSTL Class I (1.2V, 1.5V, or 1.8V) Termination 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 64: Differential Hstl Class I

    DIFF_HSTL_I DIFF_HSTL_I_18 = 0.75V for HSTL_I – 0.9V for HSTL_I_18 DIFF_HSTL_I DIFF_HSTL_I_18 50Ω ug471_c1_37_011811 Figure 1-47: Differential HSTL Class I (1.5V or 1.8V) Unidirectional Termination www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...
  • Page 65 DIFF_HSTL_I_DCI DIFF_HSTL_I_DCI_18 = 2Z 0 = 100Ω = 2Z 0 = 100Ω ug471_c1_38_021214 Figure 1-48: Differential HSTL Class I (1.5V or 1.8V) DCI Unidirectional Termination 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 66: Hstl Class Ii

    0.75V for HSTL_II_DCI 0.9V for HSTL_II_DCI_18 = 2Z 0 = 100Ω = 2Z 0 = 100Ω ug471_c1_39_121214 Figure 1-49: HSTL Class II (1.5V or 1.8V) Unidirectional Termination www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...
  • Page 67 = 2Z 0 = 100Ω = 2Z 0 = 100Ω 0.75V for HSTL_II_DCI 0.9V for HSTL_II_DCI_18 ug471_c1_40_121214 Figure 1-50: HSTL Class II (1.5V or 1.8V) Bidirectional Termination 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 68: Differential Hstl Class Ii

    0.75V for DIFF_HSTL_II – 0.9V for DIFF_HSTL_II_18 0.9V for DIFF_HSTL_II_18 DIFF_HSTL_II DIFF_HSTL_II_18 50Ω 50Ω ug471_c1_41_011811 Figure 1-51: Differential HSTL Class II (1.5V or 1.8V) Unidirectional Termination www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...
  • Page 69 = 2Z 0 = 100Ω = 2Z 0 = 100Ω = 2Z 0 = 100Ω ug471_c1_42_121214 Figure 1-52: Differential HSTL Class II (1.5V or 1.8V) DCI Unidirectional Termination 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...
  • Page 70 0.9V for DIFF_HSTL_II_18 DIFF_HSTL_II DIFF_HSTL_II DIFF_HSTL_II_18 DIFF_HSTL_II_18 50Ω 50ϖ DIFF_HSTL_II DIFF_HSTL_II DIFF_HSTL_II_18 DIFF_HSTL_II_18 – – ug471_c1_43_011811 Figure 1-53: Differential HSTL Class II (1.5V or 1.8V) Bidirectional Termination www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...
  • Page 71 – – = 2Z 0 = 100Ω = 2Z 0 = 100Ω ug471_c1_44_121214 Figure 1-54: Differential HSTL Class II (1.5V or 1.8V) DCI Bidirectional Termination 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 72: Hstl_Ii_T_Dci (1.5V Or 1.8V) Split-Thevenin Termination (3-State)

    0.9V for HSTL_II_T_DCI_18 = 2Z 0 = 100Ω 0.75V for HSTL_II_T_DCI 0.9V for HSTL_II_T_DCI_18 ug471_c1_45_021214 Figure 1-55: HSTL_II_T_DCI (1.5V) and HSTL_II_T_DCI_18 (1.8V) Split-Thevenin Termination (3-state) www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...
  • Page 73 = 2Z 0 = 100Ω – – = 2Z 0 = 100Ω ug471_c1_46_021214 Figure 1-56: Differential HSTL Class II (1.5V or 1.8V) DCI with Split-Thevenin Termination (3-state) 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 74: Sstl (Stub-Series Terminated Logic)

    I/O standards: HSTL, SSTL, HSUL, and MOBILE_DDR. This is similar to the Xilinx LVCMOS and LVTTL I/O standards, where both slow and fast slew options are available. Although slow is the default setting, for most fast interface frequencies the fast slew option is preferable.
  • Page 75 • ODT used at the memory device, if available on the bidirectional signals, and external parallel-termination resistors to V /2 where ODT is not available. 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 76: Sstl15_R, Sstl135_R, Diff_Sstl15_R, Diff_Sstl135_R

    /2) are typically placed on the board close to any receiver. The differential (DIFF_) versions use complementary single-ended drivers for outputs and differential receivers for inputs. www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 77: Sstl135_Dci

    VRN/VRP pins, creating the Thevenin equivalent resistance to the V /2 mid-point level. The differential (DIFF_) versions use complementary single-ended drivers for outputs, and differential receivers for inputs. 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 78: Sstl18, Sstl15, Sstl135, Sstl12

    0.675V for SSTL135_DCI 0.6V for SSTL12_DCI = 2Z 0 = 100Ω = 2Z 0 = 100Ω ug471_c1_47_121214 Figure 1-57: SSTL18, SSTL15, SSTL135, or SSTL12 Unidirectional Termination www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...
  • Page 79 – = 0.9V = 2Z 0 = 2Z 0 = 100Ω = 100Ω = 0.9V ug471_c1_48_121214 Figure 1-58: SSTL18, SSTL15, SSTL135, or SSTL12 Bidirectional Termination 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 80: Differential Sstl18, Sstl15, Sstl135, Sstl12

    0.675V for DIFF_SSTL135(_R) DIFF_SSTL18_(I/II) – 0.9V for DIFF_SSTL18_II 0.6V for DIFF_SSTL12 DIFF_SSTL15(_R) DIFF_SSTL135(_R) DIFF_SSTL12 50Ω 50Ω UG471_c1_49_042913 Figure 1-59: Differential SSTL18, SSTL15, SSTL135, or SSTL12 Unidirectional Termination www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...
  • Page 81 = 2Z 0 = 100Ω = 2Z 0 = 100Ω = 2Z 0 = 100Ω ug471_c1_50_121214 Figure 1-60: Differential SSTL18, SSTL15, SSTL135, or SSTL12 Unidirectional DCI Termination 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...
  • Page 82 DIFF_SSTL12 50Ω 50Ω DIFF_SSTL18_II DIFF_SSTL18_II DIFF_SSTL15(_R) DIFF_SSTL15(_R) DIFF_SSTL135(_R) DIFF_SSTL135(_R) DIFF_SSTL12 DIFF_SSTL12 – – ug471_c1_51_011811 Figure 1-61: Differential SSTL18, SSTL15, SSTL135, or SSTL12 with Bidirectional Termination www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...
  • Page 83 = 2Z 0 = 100Ω – – = 2Z 0 = 100Ω = 2Z 0 = 100Ω ug471_c1_52_121214 Figure 1-62: Differential SSTL18 Class II with DCI Bidirectional Termination 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 84: Sstl18, Sstl15, Sstl135, Or Sstl12 (T_Dci) Termination

    HSUL_12 and DIFF_HSUL_12 Table 1-37: Available I/O Bank Type Available Available The differential (DIFF_) version uses complementary single-ended drivers for outputs and differential receivers for inputs. www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 85: Hsul_Dci_12 And Diff_Hsul_12_Dci

    Example Board Topology HSUL_12 HSUL_12 – = 0.60V HSUL_12_DCI HSUL_12_DCI – = 0.60V Ω R 0 = 50 ug471_c1_54_011811 Figure 1-64: HSUL_12 with Unidirectional Signalling 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 86: Differential Hsul_12

    (with no termination) for differential HSUL_12 with unidirectional signalling. X-Ref Target - Figure 1-66 External Termination DIFF_HSUL_2 DIFF_HSUL_2 – DIFF_HSUL_2 ug471_c1_56_011811 Figure 1-66: Differential HSUL_12 with Unidirectional Signalling www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...
  • Page 87 HSUL_12 with bidirectional signalling. X-Ref Target - Figure 1-68 External Termination DIFF_HSUL_12 DIFF_HSUL_12 DIFF_HSUL_12 DIFF_HSUL_12 DIFF_HSUL_12 DIFF_HSUL_12 – – ug471_c1_58_011811 Figure 1-68: Differential HSUL_12 with Bidirectional Signalling 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 88: Mobile_Ddr (Low Power Ddr)

    MOBILE_DDR I/O standards and attributes supported. Table 1-42 lists the SLEW attribute for the 7 series FPGA single-ended and differential HSTL, SSTL, HSUL, and MOBILE_DDR I/O standards. www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...
  • Page 89 SSTL15_R SSTL15 SSTL15 SSTL15 SSTL15 SSTL15_DCI SSTL15_T_DCI SSTL18_I SSTL18_I SSTL18_I_DCI SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II_DCI SSTL18_II_DCI SSTL18_II_T_DCI HSUL_12 HSUL_12 HSUL_12 HSUL_12 HSUL_12_DCI HSUL_12_DCI MOBILE_DDR MOBILE_DDR 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...
  • Page 90 DIFF_SSTL15 DIFF_SSTL15 DIFF_SSTL15 DIFF_SSTL15 DIFF_SSTL15_DCI DIFF_SSTL15_T_DCI DIFF_SSTL18_I DIFF_SSTL18_I DIFF_SSTL18_I_DCI DIFF_SSTL18_II DIFF_SSTL18_II DIFF_SSTL18_II DIFF_SSTL18_II DIFF_SSTL18_II_DCI DIFF_SSTL18_II_DCI DIFF_SSTL18_II_T_DCI DIFF_HSUL_12 DIFF_HSUL_12 DIFF_HSUL_12 DIFF_HSUL_12 DIFF_HSUL_12_DCI DIFF_HSUL_12_DCI DIFF_MOBILE_DDR N/A DIFF_MOBILE_DDR www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 91: Lvds And Lvds_25 (Low Voltage Differential Signaling)

    (EIA/TIA compliant) LVDS signal. Receiver Termination Figure 1-70 is an example of differential termination for an LVDS or LVDS_25 receiver on a board with 50Ω transmission lines. 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...
  • Page 92 • The differential signals at the input pins meet the V requirements in the Recommended Operating Conditions table of the specific device family data sheet. www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...
  • Page 93 LVDS or BIAS LVDS_25 BIAS Input Buffer DIFF Differential 100Ω Transmission Line BIAS BIAS UG471_c1_72_050212 Figure 1-72: Example Circuit for AC-Coupled and DC-Biased Differential Clock Input 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 94: Rsds (Reduced Swing Differential Signaling)

    IBUFDS_DIFF_OUT, or OBUFDS or OBUFTDS IBUFGDS_DIFF_OUT IOSTANDARD MINI_LVDS_25 DIFF_TERM TRUE, FALSE Notes: 1. When in bidirectional configuration, internal differential termination is always used for this standard. www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 95: Ppds (Point-To-Point Differential Signaling)

    TMDS I/O standards. Table 1-52: Allowed Attributes of the TMDS I/O Standard Primitives IBUFDS, IBUFGDS, Attributes IBUFDS_DIFF_OUT, or OBUFDS or OBUFTDS IBUFGDS_DIFF_OUT IOSTANDARD TMDS _33 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 96: Blvds (Bus Lvds)

    Z 0 = 50Ω BLVDS_25 165Ω R DIV R DIFF = 100Ω BLVDS_25 140Ω Data in Z 0 = 50Ω 165Ω ug471_c1_62_011811 Figure 1-73: BLVDS Transmitter Termination www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 97: Rules For Combining I/O Standards In The Same Bank

    DCI chaining). Incompatible example: HSUL_12_DCI output with a 40Ω output impedance and SSTL12_T_DCI input with 100Ω/100Ωm split termination The implementation tools enforce these design rules. 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...
  • Page 98 DIFF_MOBILE_DDR DIFF_SSTL12 DIFF_SSTL12_DCI DIFF_SSTL12_T_DCI DIFF_SSTL135 Both 1.35 DIFF_SSTL135_R 1.35 DIFF_SSTL135_DCI 1.35 1.35 DIFF_SSTL135_T_DCI 1.35 1.35 DIFF_SSTL15 Both DIFF_SSTL15_R DIFF_SSTL15_DCI DIFF_SSTL15_T_DCI DIFF_SSTL18_I Both DIFF_SSTL18_I_DCI DIFF_SSTL18_II Both www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...
  • Page 99 0.75 HSTL_II_DCI_18 HSTL_II_T_DCI 0.75 HSTL_II_T_DCI_18 HSUL_12 Both HSUL_12_DCI LVCMOS12 Both LVCMOS15 Both LVCMOS18 Both LVCMOS25 LVCMOS33 LVDCI_15 LVDCI_18 LVDCI_DV2_15 LVDCI_DV2_18 LVDS LVDS_25 SSTL12 SSTL12_DCI SSTL12_T_DCI 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...
  • Page 100 If the voltage exceeds 2.85V, the outputs will be in a high-Z state. The device should always be operated within the recommended operating range as specified in the 7 series FPGA data sheets. www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...
  • Page 101 SLOW, FAST None None DIFF_SSTL18_I_DCI SLOW, FAST None Split DIFF_SSTL18_II Both SLOW, FAST None None DIFF_SSTL18_II_DCI SLOW, FAST Split Split DIFF_SSTL18_II_T_DCI SLOW, FAST Required None Split 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...
  • Page 102 SLOW, FAST None None SSTL12_DCI SLOW, FAST None Split SSTL12_T_DCI SLOW, FAST Required None Split LVTTL 4, 8, 12, 16, 24 SLOW, FAST None None www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...
  • Page 103 2. The DCI termination type column describes the type of termination available for the DCI I/O standards. Split refers to the split-termination resistors. 3. Internal differential termination is always used in bidirectional configuration. 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 104: Simultaneous Switching Outputs

    Similarly, a virtual V pin is created by defining an output pin driven by a logic 1 at the highest drive strength and connected to on the board. www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 105: Chapter 2: Selectio Logic Resources

    Introduction This chapter describes the logic directly behind the I/O drivers and receivers covered in Chapter 1, SelectIO Resources. 7 series FPGAs contain the basic I/O logic resources from previous Xilinx FPGAs. These resources include the following: • Combinatorial input/output •...

  • Page 106: Ilogic Resources

    BUFG/BUFGCE that is sourced in the same bank or on an adjacent bank. ZHOLD is enabled by default unless the clock source is an MMCM or PLL, or unless the IOBDELAY attribute is set in the Xilinx design constraints (XDC). Important: ZHOLD might not be appropriate for all applications, so consult the timing report to verify the impact to a specific clocking scheme.
  • Page 107 ILOGIC Resources X-Ref Target - Figure 2-3 DDLY Latch CLKB UG471_c2_01_081215 Figure 2-3: ILOGICE2 Block Diagram 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...
  • Page 108 The ILOGIC block registers have a common clock enable signal (CE1) that is active High by default. If left unconnected, the clock enable pin for any storage element defaults to the active state. www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback...

  • Page 109: Combinatorial Input Path

    Q2 on the falling edge of the clock. This structure is similar to the Virtex-6 FPGA implementation. Figure 2-5 shows the timing diagram of the input DDR using the OPPOSITE_EDGE mode. 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 110: Same_Edge Mode

    DDR using the SAME_EDGE_PIPELINED mode. The output pairs Q1 and Q2 are presented to the FPGA logic at the same time. www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 111: Input Ddr Resources (Iddr)

    DDR flip-flop. CE must be High to load new data into the DDR flip-flop. Data input (DDR) IDDR register input from IOB. 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 112: Iddr Vhdl And Verilog Templates

    ASYNC (default), SYNC clock (C) IDDR VHDL and Verilog Templates The Libraries Guide includes templates for instantiation of the IDDR primitive in VHDL and Verilog. www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 113: Ilogic Timing Models

    . The example shown uses IDDR in IDOCK IDOCKD OPPOSITE_EDGE mode. For other modes, add the appropriate latencies as shown in Figure 2-7, page 111. 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...
  • Page 114 CE1 pin Setup/Hold with respect to CLK ICE1CK ICKCE1 S/R pin Setup/Hold with respect to CLK ISRCK ICKSR D pin Setup/Hold with respect to CLK IDOCK IOCKD www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 115: Input Delay Resources (Idelay)

    IDELAYCTRL reference clock from the range specified in the 7 series FPGA data sheets. 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 116: Idelaye2 Primitive

    Output Delayed data from one of two data input ports (IDATAIN or DATAIN). CNTVALUEOUT Output Counter value going to FPGA logic for monitoring tap value. www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 117: Idelay Ports

    The CNTVALUEOUT pins are used for reporting the loaded tap value. Pipeline Register Load - LDPIPEEN When High, this input loads the pipeline register with the value currently on the CNTVALUEIN pins. 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...
  • Page 118 Individual delays can be (pipeline) loaded one at a time using LDPIPEEN and then all delays updated to their new values at the same time using the LD pin. www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback...

  • Page 119: Idelay Attributes

    HIGH_PERFORMANCE_MODE Boolean: FALSE or TRUE TRUE When TRUE, this attribute reduces the output jitter. The difference in power consumption is quantified in the Xilinx Power Estimator tool. SIGNAL_PATTERN String: DATA, CLOCK DATA Causes the timing analyzer to account for the appropriate amount of delay-chain jitter in the data or clock path.

  • Page 120: Idelay Modes

    Variable delay mode (IDELAY_TYPE = VARIABLE) In the variable delay mode, the delay value can be changed after configuration by manipulating the control signals CE and INC. When used in this mode, the www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback...

  • Page 121: Idelay Timing

    CE pin Setup/Hold with respect to C ICECK ICKCE INC pin Setup/Hold with respect to C IINCCK ICKINC LD pin Setup/Hold with respect to C IRSTCK ICKRST 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...
  • Page 122 X-Ref Target - Figure 2-13 CNTVALUEIN 5’b00010 5’b01010 5’b00010 5’b00011 5’b01010 CNTVALUEOUT DATAOUT Tap 2 Tap 3 Tap 10 UG471_c2_11_011811 Figure 2-13: IDELAY in VAR_LOAD Timing Diagram www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 123: Stability After An Increment/Decrement Operation

    IDELAY VHDL and Verilog Instantiation Template VHDL and Verilog instantiation templates are available in the Libraries Guide for all primitives and submodules. 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 124: Idelayctrl

    IDELAY and ODELAY resolution (T ). REFCLK can be supplied directly IDELAYRESOLUTION from a user-supplied source or the MMCM and must be routed on a global clock buffer. www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 125: Idelayctrl Timing

    IDELAYE2 and ODELAYE2 modules within its clock region. See the 7 Series FPGA Clocking User Guide for the definition of a clock region. Figure 2-16 illustrates the relative locations of the IDELAYCTRL modules. 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 126: Idelayctrl Usage And Design Guidelines

    Edge triggered D type flip-flop • DDR mode (SAME_EDGE or OPPOSITE_EDGE) • Level sensitive latch • Asynchronous/combinatorial Figure 2-17 illustrates the various logic resources in the OLOGIC block. www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 127: Combinatorial Output Data And 3-State Control Path

    ODDR clock, saving CLB and clock resources, and increasing performance. This mode is implemented using the DDR_CLK_EDGE attribute. It is supported for 3-state control as well. The following sections describe each of the modes in detail. 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 128: Clock Forwarding

    This is accomplished by tying the D1 input of the ODDR primitive High, and the D2 input Low. Xilinx recommends using this scheme to forward clocks from the FPGA logic to the output pins.

  • Page 129: Output Ddr Primitive (Oddr)

    Set/Reset type with respect to clock (C) ASYNC, SYNC (default) ODDR VHDL and Verilog Templates The Libraries Guide includes templates for instantiation of the ODDR module in VHDL and Verilog. 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 130: Ologic Timing Models

    Clock Event 1, the output clock enable signal becomes OOCECK valid-high at the OCE input of the output register, enabling the output register for incoming data. www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...
  • Page 131 ODDR register, reflected at the OQ output at time T after Clock Event 9 (no change at the OQ output in this case) and 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...
  • Page 132 Clock Event 2, the S/R signal (configured as synchronous reset OSRCK in this case) becomes valid-high, resetting the 3-state register at time T after Clock Event 2. www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...
  • Page 133 3-state Register, reflected at the TQ output at time T after Clock Event 10 (no change at the TQ output in this case). 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 134: Output Delay Resources (Odelay)-Not Available In Hr Banks

    Dynamically inverts the clock (C) polarity. CNTVALUEIN Input Input value from FPGA logic for dynamically loadable tap value. CLKIN Input Clock Access into the ODELAY (from the I/O CLKMUX). www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 135: Odelay Ports

    When in VAR_LOAD_PIPE mode, the IDELAY load port, LD, loads the value currently in the pipeline register. The value present in the pipeline register will be the new tap value. 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...
  • Page 136 Individual delays might be (pipeline) loaded one at a time using LDPIPEEN and then all delays updated to their new values at the same time using the LD pin. www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback...

  • Page 137: Odelay Attributes

    HIGH_PERFORMANCE_MODE Boolean: FALSE or FALSE When TRUE, this attribute reduces the output TRUE jitter. The difference in power consumption is quantified in the Xilinx Power Estimator tool. SIGNAL_PATTERN String: DATA, DATA Causes the timing analyzer to account for the CLOCK appropriate amount of delay-chain jitter in the data or clock path.

  • Page 138: Odelay Modes

    Table 2-6. Table 2-15: Control Pin when ODELAY_TYPE = VARIABLE TAP Setting No Change ODELAY_VALUE No Change Current Value +1 Current Value –1 No Change www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 139: Odelay Timing

    ODELAYE2 (ODELAY_TYPE = VARIABLE, ODELAY_VALUE = 0, and DELAY_SRC = CLKIN/ODATAIN) timing diagram. X-Ref Target - Figure 2-26 DATAOUT Tap 0 Tap 1 UG471_c2_24_011811 Figure 2-26: ODELAY Timing Diagram (VARIABLE Mode) 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...
  • Page 140 CNTINVALUE. The CNTVALUEOUT shows the value of the tap setting. The output will remain at tap 10 indefinitely until there is further activity on the LD, CE, or INC pins. www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback...

  • Page 141: Stability After An Increment/Decrement Operation

    Each part of the template should be inserted within the VHDL design file. The port map of the architecture section should include the design signals names. 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...
  • Page 142 Chapter 2: SelectIO Logic Resources www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 143: Chapter 3: Advanced Selectio Logic Resources

    FPGA fabric. This can be used for training source-synchronous interfaces that include a training pattern. • Dedicated support for strobe-based memory interfaces 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...
  • Page 144 X-Ref Target - Figure 3-1 DDLY SHIFTIN1/2 Multiplexers SHIFTOUT1/2 Q1:Q8 Module DYNCLKSEL Serial-to- CLKB Parallel Converter OCLK DYNCLKDIVSEL CLKDIV CLKDIVP Bitslip Module BITSLIP UG471_c3_01_080210 Figure 3-1: ISERDESE2 Block Diagram www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 145: Iserdese2 Primitive (Iserdese2)

    Serial input data from IOB. See Serial Input Data from IOB - DDLY Input Serial input data from IDELAYE2. See Serial Input Data from IDELAYE2 - DDLY. 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 146: Iserdese2 Ports

    ISERDESE2 block. When width expansion is used, D1 of the transmitter OSERDESE2 is the least significant input, while Q8 of the receiver ISERDESE2 block is the least significant output. www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 147: Combinatorial Output - O

    SDR). See BITSLIP Submodule for more details. Clock Enable Inputs - CE1 and CE2 Each ISERDESE2 block contains an input clock enable module (Figure 3-4). 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 148: High-Speed Clock Input - Clk

    The serial input data port (D) is the serial (high-speed) data input port of the ISERDESE2. This port works in conjunction only with the 7 series FPGA IOB resource. See Using D and DDLY in the ISERDESE2. www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 149: Serial Input Data From Idelaye2 - Ddly

    CLKDIV are stable and present, and should be a minimum of two CLKDIV pulses wide. After deassertion of reset, the output is not valid until after two CLKDIV cycles. 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 150: Iserdese2 Attributes

    ISERDESE2 attributes. A detailed description of each attribute follows the table. For more information on applying these attributes in UCF, VHDL, or Verilog code, refer to the Xilinx ISE Software Manual. Table 3-2: ISERDESE2 Attributes Default...

  • Page 151: Data_Rate Attribute

    The allowed values for this attribute are MEMORY, MEMORY_DDR3, MEMORY_QDR, OVERSAMPLE, or NETWORKING. The default mode is MEMORY. Figure 3-5 illustrates the ISERDESE2 internal connections when in MEMORY mode. 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 152: Num_Ce Attribute

    ISERDESE2 inputs, then although the clocking arrangement is an allowed BUFIO/BUFR configuration, the clocks would still be out of phase. This also prohibits using DYNCLKINVSEL and DYNCLKDIVINVSEL. www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 153: Memory Interface Type

    OCLK but is clocked out of the ISERDESE2 on the CLK domain. CLKDIV is not used in this mode. The only valid clocking arrangements for the OVERSAMPLE interface type are: 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...
  • Page 154 OCLK OCLKB Sample 4 CLKDIV DYNCLKSEL DYNCLKDIVSEL SHIFTIN1 ISERDESE2 Primitive SHIFTOUT1 SHIFTIN2 SHIFTOUT2 BITSLIP UG471_c3_07_021914 Figure 3-7: Logical View of ISERDESE2 Primitive in Oversample Mode www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 155: Memory_Ddr3 Interface Type

    Set the SERDES_MODE attribute for the master ISERDESE2 to MASTER and the slave ISERDESE2 to SLAVE. See SERDES_MODE Attribute. The user must connect the SHIFTIN ports of the SLAVE to the SHIFTOUT ports of the MASTER. 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 156: Iserdese2 Latencies

    By using the ISERDESE2 as a feedback port, it can not be used as an input for external data. X-Ref Target - Figure 3-9 ISERDESE2 OSERDESE2 ug471_c3_09_012211 Figure 3-9: ISERDESE2 and OSERDESE2 Connected via the OFB Port www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 157: Using D And Ddly In The Iserdese2

    Figure 3-10 illustrates an ISERDESE2 timing diagram for the input data to the ISERDESE2. The timing parameter names change for different modes (SDR/DDR). However, the 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 158: Iserdese2 Vhdl And Verilog Instantiation Template

    The Bitslip operation is synchronous to CLKDIV. In SDR mode, every Bitslip operation causes the output pattern to shift left by one. In DDR mode, every Bitslip operation causes the output pattern to alternate between www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback...
  • Page 159 Bitslip command. If the ISERDESE2 is reset, the Bitslip logic is also reset and returns back to its initial state. 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 160: Bitslip Timing Model And Parameters

    Q4-Q1. After a third shift (one position right), the output DABC is available on Q4-Q1. After a fourth shift (three positions left), the original output CDAB is available on Q4-Q1, and Bitslip has finished cycling through all four input combinations. www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback...

  • Page 161: Output Parallel-To-Serial Logic Resources (Oserdese2)

    Prior to use, a reset must be applied to the OSERDESE2. The OSERDESE2 contains an internal counter that controls dataflow. Failure to synchronize the reset deassertion with the CLKDIV will produce an unexpected output. 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 162: 3-State Parallel-To-Serial Conversion

    The OSERDESE2 primitive is shown in Figure 3-14. X-Ref Target - Figure 3-14 CLKDIV TBYTEOUT SHIFTOUT1 SHIFTOUT2 OSERDESE2 Primitive TBYTEIN SHIFTIN1 SHIFTIN2 UG471_c3_14_041712 Figure 3-14: OSERDESE2 Primitive www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 163: Oserdese2 Ports

    OSERDESE2 for use with the ODELAYE2 primitive, or the OFB port can be used to send out serial data to the ISERDESE2. See Output Feedback. 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 164: 3-State Control Output - Tq

    FPGA fabric. They can be configured as one, two, or four bits, or bypassed. The behavior of these ports is controlled by the DATA_RATE_TQ and TRISTATE_WIDTH attributes. www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback...

  • Page 165: Oserdese2 Attributes

    SDR and DDR mode registers are bypassed, and therefore, the T1 input should be used. The signal applied to the T1 input is asynchronous to all other signals because it simply passes through the OSERDESE2. 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 166: Data_Rate_Oq Attribute

    When using a MMCM to drive the CLK and CLKDIV of the OSERDESE2 the buffer types suppling the OSERDESE2 can not be mixed. For example, if CLK is driven by a BUFG, CLKDIV must be driven by a BUFG as well. www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback...

  • Page 167: Oserdese2 Width Expansion

    SERDES_MODE = MASTER Data Out OSERDESE2 Data Inputs[0:7] (Master) SHIFTIN1 SHIFTIN2 SHIFTOUT1 SHIFTOUT2 OSERDESE2 Data Inputs[8:9] (Slave) SERDES_MODE=SLAVE ug471_c3_15_111011 Figure 3-15: Block Diagram of OSERDESE2 Width Expansion 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 168: Guidelines For Expanding The Parallel-To-Serial Converter Bit Width

    (a) when the rising edge of CLKDIV clocks the data at inputs D1–D8 into the OSERDESE2, and (b) when the first bit of the serial stream appears at OQ. Table 3-11 summarizes the various OSERDESE2 latency values. www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 169: Oserdese2 Timing Model And Parameters

    Clock to Out from CLK to OQ OSCKO_OQ Clock to Out from CLK to TQ OSCKO_TQ Combinatorial Asynchronous Reset to OQ OSCO_OQ Asynchronous Reset to TQ OSCO_TQ 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 170: Timing Characteristics Of 2:1 Sdr Serialization

    The data bit A appears at OQ one CLK cycle after AB is sampled into the OSERDESE2. This latency is consistent with the Table 3-11 listing of a 2:1 SDR mode OSERDESE2 latency of one CLK cycle. www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 171: Timing Characteristics Of 8:1 Ddr Serialization

    Table 3-11 listing of a 8:1 DDR mode OSERDESE2 latency of four CLK cycles. The second word IJKLMNOP is sampled into the OSERDESE2 from the D1–D8. 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 172: Timing Characteristics Of 4:1 Ddr 3-State Controller Serialization

    T1–T4 and D1–D4 in the OSERDESE2 are identical (including latency), such that the bits EFGH are always aligned with the 0010 presented at the T1–T4 pins during Clock Event 1. www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback...

  • Page 173: Oserdese2 Vhdl And Verilog Instantiation Templates

    FIFOs or LUT-based FIFOs. IO_FIFOs support standard flag logic, clocks, and control signals. IO_FIFOs can operate in two modes, 4 x 4 mode (1:1) or 4 x 8/8 x 4 mode (1:2/2:1). 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 174: In_Fifo

    Table 3-13: IN_FIFO Input to Output Data Mapping in 4 x 4 Mode Mapping Not Used D0[3:0] → Q0[3:0] Q0[7:4] D1[3:0] → Q1[3:0] Q1[7:4] D2[3:0] → Q2[3:0] Q2[7:4] D3[3:0] → Q3[3:0] Q3[7:4] D4[3:0] → Q4[3:0] Q4[7:4] www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 175: In_Fifo Primitive

    D8[3:0] → Q8[7:0] D9[3:0] → Q9[7:0] Both modes support the FULL, EMPTY, ALMOSTFULL, and ALMOSTEMPTY flags. IN_FIFO Primitive The IN_FIFO primitive is shown in Figure 3-20. 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...
  • Page 176 Ten 8-bit data out buses in 4 x 8 mode, or ten 4-bit data out buses in 4 x 4 mode. Connect to fabric if used for external interfaces. www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 177: Out_Fifo

    10 4-bit wide data outputs (Q). In 8 x 4 mode, a 2:1 multiplexer in the output datapath serializes the 8-bit input data to the 4-bit output data width. 4 x 8 mode is generally 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 178: Out_Fifo Primitive

    D8[7:0] → Q8[3:0] D9[7:0] → Q9[3:0] Both modes support the FULL, EMPTY, ALMOSTFULL, and ALMOSTEMPTY flags. OUT_FIFO Primitive The OUT_FIFO primitive is shown in Figure 3-21. www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...
  • Page 179 Q5[7:4] and Q6[7:4]. RDEN Read enable. WREN Write enable. Q0[3:0] – Q9[3:0] Ten 4-bit data output buses. Connect to OLOGIC if used for external interfaces. 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...

  • Page 180: Resetting The Io_Fifo

    EMPTY flags. It is possible to have ALMOSTEMPTY assert and deassert before EMPTY asserts. This will occur if WRCLK is more than two times faster than RDCLK. Table 3-19 summarizes all the applicable IO_FIFO attributes. www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...
  • Page 181 ALMOST EMPTY and ALMOST FULL Flags, page 180. OUTPUT_DISABLE Boolean: TRUE or FALSE OUT_FIFO: Output disable drives the FALSE Qx outputs High when RD_EN is low. 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...
  • Page 182 Chapter 3: Advanced SelectIO Logic Resources www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...
  • Page 183 Far V 50Ω HSTL_II_T_DCI_18 Far V 50Ω HSUL_12 None HSUL_12_DCI None LVCMOS (all voltages) None LVTTL (2 mA, 4 mA, 6 mA, and 8 mA drive) 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...
  • Page 184 None LVDCI_DV2_18 None LVDS Far Differential 100Ω LVDS_25 Far Differential 100Ω MINI_LVDS_25 Far Differential 100Ω PCI33_3 None PPDS_25 Far Differential 100Ω RSDS_25 Far Differential 100Ω www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...
  • Page 185 1. All differential versions of the HSTL, SSTL, HSUL, and MOBILE_DDR standards (e.g., DIFF_SSTL135) have the same termination as the single-ended versions. Figure A-1 illustrates each of these terminations. 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...
  • Page 186 100 70 Z=50 1KFar-end Parallel Termination to 3.3V FP_3.3_1000 3.3V 1K Z=50 50Far-end Parallel Termination to V FP_VTT_50 50 Z=50 ug471_aA_01_050212 Figure A-1: Default Terminations www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...
  • Page 187 7 Series FPGAs SelectIO Resources User Guide www.xilinx.com Send Feedback UG471 (v1.10) May 8, 2018...
  • Page 188 Appendix A: Termination Options for SSO Noise Analysis www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide Send Feedback UG471 (v1.10) May 8, 2018...

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