Match_Cycle Configuration Option; Dciupdatemode Configuration Option - Xilinx SelectIO 7 Series User Manual

For controlled impedance output drivers, the impedance can be adjusted either to match
the reference resistors or half the resistance of the reference resistors. For on-chip
termination, the termination is always adjusted to match the reference resistors.
For the I/O standards that support the DCI controlled impedance driver, DCI can
configure output drivers to be the following types:
•
•
For the I/O standards that support parallel termination, DCI creates a Thevenin
equivalent, or split-termination resistance, to the V
naming convention adds:
•
•

Match_cycle Configuration Option

Match_cycle is a configuration option that optionally halts the startup sequence at the end
of the FPGA configuration sequence until the DCI logic has performed the first match
(calibration) to the external reference resistors. This option is also sometimes referred to as
DCI match. For more information about the Match_cycle option, refer to the
"Configuration Details" chapter in UG470: 7 Series FPGAs Configuration User Guide. For
information on how to invoke the option in a design and to set it to a specific startup cycle,
refer to the Match_cycle option in UG628: Command Line Tools User Guide.

DCIUpdateMode Configuration Option

DCIUpdateMode is a configuration option that can override control of how often the DCI
circuit updates the impedance matching to the VRN and VRP reference resistors. This
option defaults to AsRequired but also has an optional value of Quiet in the Xilinx
implementation software. The settings for the DCIUpdateMode configuration option are:
•
•
•
It is strongly recommended that the DCIUpdateMode option be kept with the default
value of AsRequired so that the DCI circuitry is allowed to operate normally. See
UG628: Command Line Tools User Guide for more details if there is a special need to set this
option to Quiet.
7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
Controlled Impedance Driver (Source Termination)
Controlled Impedance Driver with Half Impedance (Source Termination)
DCI in the name of the I/O standard if split-termination resistors are always present
in the I/O, independent of whether the standard is used on an input, output, or
bidirectional pin.
T_DCI in the name of the I/O standard if split-termination resistors are only present
when the output buffer is 3-stated.
AsRequired: Initial impedance calibration is made at device initialization, and
dynamic impedance adjustments are made as needed throughout device operation
(default).
Continuous: For 7 series FPGAs, this value has no effect (defaults back to
AsRequired).
Quiet: Impedance calibration is done only once at device initialization, or each time
the RST pin is asserted on the DCIRESET primitive for designs that include this
primitive.
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7 Series FPGA DCI—Only available in the HP I/O banks
/2 voltage level. The I/O standards'
CCO
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