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Chapter 3:
Advanced SelectIO Logic Resources
Bitslip Timing Model and Parameters
This section discusses the timing models associated with the Bitslip controller in a 1:4 DDR
configuration. Data (D) is a repeating, 4-bit training pattern ABCD. ABCD could appear at
the parallel outputs Q1–Q4 of the ISERDESE2 in four possible ways: ABCD, BCDA, CDAB,
and DABC. Only one of these four alignments of the parallel word makes sense to the
user's downstream logic that reads the data from the Q1–Q4 outputs of the ISERDESE2. In
this case, ABCD is assumed to be the word alignment that makes sense. Asserting Bitslip
allows the user to see all possible configurations of the input data and then choose the
required alignment (ABCD).
corresponding re-alignments of the ISERDESE2 parallel outputs Q1–Q4.
X-Ref Target - Figure 3-12
Clock Event 1
The entire first word CDAB has been sampled into the input side registers of the
ISERDESE2. The Bitslip pin is not asserted; the word propagates through the ISERDESE2
without any realignment.
Clock Event 2
The Bitslip pin is asserted, which causes the Bitslip controller to shift all bits internally by
one bit to the right. Bitslip is held High for one (only one) CLKDIV cycle.
Clock Event 3
Three CLKDIV cycles after asserting Bitslip, the Bitslip operation is completed and the new
shifted data is available on the output as BCDA.
After Clock Event 3
Bitslip can be usefully asserted up to two more times as the ISERDESE2 is configured for
1:4. After the second shift (three positions left as this DDR), the (required) output ABCD is
available on Q4-Q1. After a third shift (one position right), the output DABC is available on
Q4-Q1. After a fourth shift (three positions left), the original output CDAB is available on
Q4-Q1, and Bitslip has finished cycling through all four input combinations.
160
Send Feedback
Figure 3-12
1
D A B
C D A B C D
D
CLK
BITSLIP
CLKDIV
Q4–Q1
CDAB
Figure 3-12: DDR Bitslip Functional Diagram
www.xilinx.com
shows the timing of a Bitslip operation and the
2
A B C D A B
A B
C D
C D
Bitslip
7 Series FPGAs SelectIO Resources User Guide
3
A B
C D
A B
C
BCDA
ug471_c3_12_042111
UG471 (v1.10) May 8, 2018
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