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X-Ref Target - Figure 2-7
C
CE
D0A D1A D2A
D
Q1
Q2
Figure 2-7: Input DDR Timing in SAME_EDGE_PIPELINED Mode
Input DDR Resources (IDDR)
Figure 2-8
at the same time.
attributes available and default values for the IDDR primitive.
X-Ref Target - Figure 2-8
Table 2-1: IDDR Port Signals
Q1 and Q2
C
CE
D
7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
D3A D4A D5A D6A D7A D8A D9A D10A D11A D12A D13A
D0A
D2A
D1A
D3A
shows the block diagram of the IDDR primitive. Set and Reset are not supported
Table 2-1
lists the IDDR port signals.
Figure 2-8: IDDR Primitive Block Diagram
Port
Function
Name
Data outputs
Clock input port
Clock enable port
Data input (DDR)
www.xilinx.com
D4A
D6A
D5A
D7A
Table 2-2
D
Q1
IDDR
Q2
CE
C
S/R
ug471_c2_06_061215
Description
IDDR register outputs.
The C pin represents the clock input pin.
The enable pin affects the loading of data into the DDR
flip-flop. When Low, clock transitions are ignored and
new data is not loaded into the DDR flip-flop. CE must be
High to load new data into the DDR flip-flop.
IDDR register input from IOB.
ILOGIC Resources
D8A
D10A
D9A
D11A
ug471_c2_05_090810
describes the various
111
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