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Chapter 1:
SelectIO Resources
Table 1-55: V
and V
CCO
I/O Standard
LVTTL
MINI_LVDS_25
MOBILE_DDR
PCI33_3
PPDS_25
RSDS_25
SSTL135
SSTL135_R
SSTL135_DCI
SSTL135_T_DCI
SSTL15
SSTL15_R
SSTL15_DCI
SSTL15_T_DCI
SSTL18_I
SSTL18_I_DCI
SSTL18_II
SSTL18_II_DCI
SSTL18_II_T_DCI
TMDS_33
Notes:
1.
Differential inputs for these standards can be placed in banks with V
outputs. There are some important criteria that need to be considered:
a.
The optional internal differential termination is not used (DIFF_TERM = FALSE, which is the default value) unless the V
voltage is at the level required for outputs.
b.
The differential signals at the input pins meet the V
specific device family data sheet.
c.
The differential signals at the input pins meet the V
Specifications tables in the specific device family data sheet. In some cases, to accomplish this it might be necessary to provide
an external circuit to both AC-couple and DC-bias the pins.
2.
If the voltage exceeds 2.85V, the outputs will be in a high-Z state. The device should always be operated within the recommended
operating range as specified in the 7 series FPGA data sheets.
100
Send Feedback
Requirements for Each Supported I/O Standard (Cont'd)
REF
I/O Bank
Availability
Output
HR
3.3
(2)
HR
2.5
HR
1.8
HR
3.3
(2)
HR
2.5
(2)
HR
2.5
Both
1.35
HR
1.35
HP
1.35
HP
1.35
Both
1.5
HR
1.5
HP
1.5
HP
1.5
Both
1.8
HP
1.8
Both
1.8
HP
1.8
HP
1.8
HR
3.3
www.xilinx.com
V
(V)
CCO
Input
DIFF_TERM = TRUE
3.3
(1)
2.5
1.8
3.3
(1)
2.5
(1)
2.5
Any
Any
1.35
1.35
Any
Any
1.5
1.5
Any
1.8
Any
1.8
1.8
Any
levels that are different from the required level for
CCO
requirements in the Recommended Operating Conditions table of the
IN
and V
requirements in the corresponding LVDS or LVDS_25 DC
IDIFF
ICM
7 Series FPGAs SelectIO Resources User Guide
V
REF
Input with
Input
N/A
N/A
2.5
N/A
N/A
N/A
N/A
N/A
2.5
N/A
2.5
N/A
N/A
0.675
N/A
0.675
N/A
0.675
N/A
0.675
N/A
0.75
N/A
0.75
N/A
0.75
N/A
0.75
N/A
0.9
N/A
0.9
N/A
0.9
N/A
0.9
N/A
0.9
N/A
N/A
UG471 (v1.10) May 8, 2018
(V)
CCO
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