Xilinx SelectIO 7 Series User Manual page 154

Chapter 3: Advanced SelectIO Logic Resources
• CLK and CLKB are driven by a BUFIO. OCLK and OCLKB are driven by a BUFIO that is
phase shifted by 90°. The two BUFIOs are driven from a single MMCM.
• CLK and CLKB are driven by a BUFG. OCLK and OCLKB are driven by a BUFG that is
phase shifted by 90°. The BUFGs are driven from a single MMCM. In either case, the
effective clocking is:
X-Ref Target - Figure 3-7
DDLY
CLK
CLKB
CE2
CE1
OCLK
OCLKB
CLKDIV
DYNCLKSEL
DYNCLKDIVSEL
SHIFTIN1
SHIFTIN2
RST
D
BITSLIP
OFB
Figure 3-7: Logical View of ISERDESE2 Primitive in Oversample Mode
154
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• CLK: 0°
• OCLK: 90°
• CLKB: 180°
• OCLKB: 270°
D Q
REG
CLK
D Q
REG
CLK
D Q
REG
CLK
D Q
REG
CLK
ISERDESE2
Primitive
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D Q D Q
REG REG
CLK CLK
D Q D Q
REG REG
CLK CLK
D Q D Q
REG REG
CLK CLK
D Q D Q
REG REG
CLK CLK
7 Series FPGAs SelectIO Resources User Guide
Q1
Sample 1
Q2
Sample 3
Q3
Sample 2
Q4
Sample 4
Q5
Q6
Q7
Q8
SHIFTOUT1
SHIFTOUT2
O
UG471_c3_07_021914
UG471 (v1.10) May 8, 2018