Iobufds_Diff_Out_Dcien - Xilinx SelectIO 7 Series User Manual

X-Ref Target - Figure 1-29

IOBUFDS_DIFF_OUT_DCIEN

The IOBUFDS_DIFF_OUT_DCIEN primitive shown in
I/O banks. It has complementary differential outputs, an IBUFDISABLE port that can be
used to disable the input buffer during periods that the buffer is not being used, and a
DCITERMDISABLE port that can be used to manually disable the optional DCI
split-termination feature. See
VCCO/2)
X-Ref Target - Figure 1-30
The IOBUFDS_DIFF_OUT_DCIEN primitive can disable the input buffer and force both
the O and OB outputs to the fabric High when the USE_IBUFDISABLE attribute is set to
TRUE and the IBUFDISABLE signal is asserted High. If USE_IBUFDISABLE is set to
FALSE, this input is ignored and should be tied to ground. If the I/O is using the
7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
3-state input from
master OLOGIC
Input from FPGA
Output to FPGA
3-state input from
slave OLOGIC
Figure 1-29: Differential Input/Output Buffer Primitive With Complementary
Outputs for the Input Buffer (IOBUFDS_DIFF_OUT)
and DCI and 3-state DCI (T_DCI)
IBUFDISABLE
DCITERMDISABLE
Figure 1-30: Differential Bidirectional Buffer with Complementary Outputs, Input
Path Disable, and DCI Disable (IOBUFDS_DCIEN)
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7 Series FPGA SelectIO Primitives
IOBUFDS_DIFF_OUT
TM
IO
I
O
OB
IOB
TS
Split-Termination DCI (Thevenin Equivalent Termination to
for more details.
IOBUFDS_DIFF_OUT_DCIEN
I
TS
TM
O
OB
To/From Device Pad
ug471_c1_26_041112
Figure 1-30 is available in the HP
IO
IOB
UG471_c1_70_021214
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