Xilinx SelectIO 7 Series User Manual page 87

Figure 1-67
differential HSUL_12 with unidirectional DCI signalling.
X-Ref Target - Figure 1-67
DIFF_HSUL_12_DCI
R 0 = 50
DIFF_HSUL_12_DCI
R 0 = 50
Figure 1-67: Differential HSUL_12 with Unidirectional DCI Signalling
Figure 1-68
differential HSUL_12 with bidirectional signalling.
X-Ref Target - Figure 1-68
External Termination
DIFF_HSUL_12
DIFF_HSUL_12
DIFF_HSUL_12
Figure 1-68: Differential HSUL_12 with Bidirectional Signalling
7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
shows a sample circuit illustrating a board topology (with no termination) for
DCI
IOB
Ω
Ω
shows a sample circuit illustrating a board topology (with no termination) for
IOB
+
–
www.xilinx.com
Supported I/O Standards and Terminations
IOB
Z 0
DIFF_HSUL_12_DCI
+
–
Z 0
IOB
Z 0
Z 0
ug471_c1_57_0111811
DIFF_HSUL_12
DIFF_HSUL_12
DIFF_HSUL_12
+
–
ug471_c1_58_011811
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