Ologic Timing Models; Timing Characteristics - Xilinx SelectIO 7 Series User Manual

Chapter 2: SelectIO Logic Resources

OLOGIC Timing Models

This section discusses all timing models associated with the OLOGIC block.
describes the function and control signals of the OLOGIC switching characteristics in the
7 series FPGA data sheets.
Table 2-12: OLOGIC Switching Characteristics
Setup/Hold
T
T
T
T
T
Clock to Out
T
T

Timing Characteristics

Figure 2-21
X-Ref Target - Figure 2-21
Clock Event 1
•
130
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Symbol
/T D1/D2 pins Setup/Hold with respect to CLK
ODCK OCKD
/T OCE pin Setup/Hold with respect to CLK
OOCECK OCKOCE
/T S/R pin Setup/Hold with respect to CLK
OSRCK OCKSR
/T T1/T2 pins Setup/Hold with respect to CLK
OTCK OCKT
/T TCE pin Setup/Hold with respect to CLK
OTCECK OCKTCE
CLK to OQ/TQ out
OCKQ
S/R pin to OQ/TQ out
RQ
illustrates the OLOGIC output register timing.
1
CLK
T
ODCK
D1
T
OOCECK
OCE
S/R
OQ
Figure 2-21: OLOGIC Output Register Timing Characteristics
At time T before Clock Event 1, the output clock enable signal becomes
OOCECK
valid-high at the OCE input of the output register, enabling the output register for
incoming data.
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Description
2 3
T
OCKQ
7 Series FPGAs SelectIO Resources User Guide
Table 2-12
4 5
T
OSRCK
ug471_c2_19_081215
UG471 (v1.10) May 8, 2018