Timing Characteristics Of 4:1 Ddr 3-State Controller Serialization - Xilinx SelectIO 7 Series User Manual

Chapter 3: Advanced SelectIO Logic Resources
Clock Event 4
Between Clock Events 3 and 4, the entire word ABCDEFGH is transmitted serially on OQ,
a total of eight bits transmitted in one CLKDIV cycle.
The data bit I appears at OQ four CLK cycles after IJKLMNOP is sampled into the
OSERDESE2. This latency is consistent with the
OSERDESE2 latency of four CLK cycles.

Timing Characteristics of 4:1 DDR 3-State Controller Serialization

The operation of a 3-state controller is illustrated in
case shown in a bidirectional system where the IOB must be frequently 3-stated.
X-Ref Target - Figure 3-18
Clock Event 1
T1, T2, and T4 are driven Low to release the 3-state condition. The serialization paths of
T1–T4 and D1–D4 in the OSERDESE2 are identical (including latency), such that the bits
EFGH are always aligned with the 0010 presented at the T1–T4 pins during Clock Event 1.
172
Send Feedback
D1 A
D2
B
D3
C
D4 D
CLKDIV
CLK
T1 1
T2 1
1
T3
T4 1
OQ
TQ
OBUFT.O
Figure 3-18: OSERDESE2 Data Flow and Latency in 4:1 DDR Mode
www.xilinx.com
Table 3-11 listing of a 8:1 DDR mode
Figure 3-18. The example is a 4:1 DDR
Clock Clock
Event 1 Event 2
E I
F J
G K
H L
0
0
1
0
A B C D E F G H
E F H
7 Series FPGAs SelectIO Resources User Guide
1
1
1
1
I J K L
UG471_c3_18_021914
UG471 (v1.10) May 8, 2018