Lvcmos (Low Voltage Cmos) - Xilinx SelectIO 7 Series User Manual

Chapter 1: SelectIO Resources

LVCMOS (Low Voltage CMOS)

Table 1-11: Available I/O Bank Type
LVCMOS is a widely used switching standard implemented in CMOS transistors. This
standard is defined by JEDEC (JESD 8C.01). The LVCMOS standards supported in 7 series
FPGAs are: LVCMOS12, LVCMOS15, LVCMOS18, LVCMOS25, and LVCMOS33.
Sample circuits illustrating both unidirectional and bidirectional LVCMOS termination
techniques are shown in
of source-series and parallel terminated topologies.
Figure 1-39
X-Ref Target - Figure 1-39
54
Send Feedback
HR HP
Available Available
Figure 1-39
shows unidirectional terminated topologies.
IOB
LVCMOS
IOB
LVCMOS
R S = Z 0 – R D
IOB
LVCMOS
Note: V
TT
Figure 1-39: LVCMOS Unidirectional Termination
www.xilinx.com
and Figure 1-40. These two diagrams show examples
IOB
LVCMOS
Z 0
IOB
LVCMOS
Z 0
V
TT
IOB
LVCMOS
R P = Z 0
Z 0
is any voltage from 0V to V CCO
7 Series FPGAs SelectIO Resources User Guide
ug471_c1_29_011811
UG471 (v1.10) May 8, 2018