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Chapter 3:
Advanced SelectIO Logic Resources
Table 3-1: ISERDESE2 Port List and Definitions (Cont'd)
Port Name
Type
CLK
Input
CLKB
Input
CE1, CE2
Input
RST
Input
CLKDIV
Input
CLKDIVP
Input
OCLK
Input
OCLKB
Input
BITSLIP
Input
SHIFTIN1
Input
SHIFTIN2
Input
OFB
Input
DYNCLKDIVSEL
Input
DYNCLKSEL
Input
ISERDESE2 Ports
Registered Outputs – Q1 to Q8
The output ports Q1 to Q8 are the registered outputs of the ISERDESE2 module. One
ISERDESE2 block can support up to eight bits (i.e., a 1:8 deserialization). Bit widths greater
than eight (up to 14) can be supported in DDR mode only. See
The first data bit received appears on the highest order Q output.
The bit ordering at the input of an OSERDESE2 is the opposite of the bit ordering at the
output of an ISERDESE2 block, as shown in
bit A of the word FEDCBA is placed at the D1 input of an OSERDESE2, but the same bit A
emerges from the ISERDESE2 block at the Q8 output. In other words, D1 is the least
significant input to the OSERDESE2, while Q8 is the least significant output of the
ISERDESE2 block. When width expansion is used, D1 of the transmitter OSERDESE2 is the
least significant input, while Q8 of the receiver ISERDESE2 block is the least significant
output.
146
Send Feedback
Width
1
High-speed clock input. Clocks serial input data stream. See
Clock Input -
CLK.
1
Second High speed clock input only for MEMORY_QDR mode. Always
connect to inverted CLK unless in MEMORY_QDR mode. See
MEMORY_QDR Interface
1 (each)
Clock enable inputs. See
1
Active High reset. See
1
Divided clock input. Clocks delay element, deserialized data, Bitslip
submodule, and CE unit. See
1
Only supported via the MIG tool. Sourced by PHASER_IN divided CLK in
MEMORY_DDR3 mode. All other modes connect to ground.
1
High-speed clock input for memory applications. See
Strobe-Based Memory Interfaces and Oversampling Mode -
clock resource is shared with the OSERDESE2 CLK pin.)
1
Inverted high-speed clock input. (This clock resource is shared with the
OSERDESE2 CLKB pin.)
1
Invokes the Bitslip operation. See
1
Carry input for data width expansion. Connect to SHIFTOUT1 of master IOB.
See
ISERDESE2 Width
1
Carry input for data width expansion. Connect to SHIFTOUT2 of master IOB.
See
ISERDESE2 Width
1
Feedback Path from the OLOGICE2 or OLOGICE3 and OSERDESE2 output.
See
ISERDESE2 Feedback from
1
Dynamically select CLKDIV inversion. See
1
Dynamically select CLK and CLKB inversion. See
www.xilinx.com
Description
Type.
Clock Enable Inputs - CE1 and
Reset Input -
RST.
Divided Clock Input -
Bitslip Operation -
Expansion.
Expansion.
OSERDESE2.
Dynamic Clock
ISERDESE2 Width Expansion
Figure
3-3. For example, the least significant
7 Series FPGAs SelectIO Resources User Guide
High-Speed
CE2.
CLKDIV.
High-Speed Clock for
OCLK. (This
BITSLIP.
Inversions.
Dynamic Clock
Inversions.
.
UG471 (v1.10) May 8, 2018
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