Idelay Timing - Xilinx SelectIO 7 Series User Manual

Table 2-6: Control Pin when IDELAY_TYPE = VARIABLE
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Table 2-7: Control Pin when IDELAY_TYPE = VAR_LOAD

IDELAY Timing

Table 2-8
Table 2-8: IDELAY Switching Characteristics
T
T
T
T
7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
IDELAYCTRL primitive must be instantiated. See
Guidelines for more details. The control pins being used in VARIABLE mode are
described in Table 2-6.
C LD CE INC
0 x x x
1 1 x x
1 0 0 x
1 0 1 1
1 0 1 0
1 0 0 0
Loadable variable delay mode (IDELAY_TYPE = VAR_LOAD)
In addition to having the same functionality of (IDELAY_TYPE = VARIABLE) in this
mode the IDELAY tap can be loaded via the 5-input bits CNTVALUEIN<4:0> from the
FPGA logic. When LD is pulsed the value present at CNTVALUEIN<4:0> will be the
new tap value. As a results of this functionality the IDELAY_VALUE attribute is
ignored. When used in this mode, the IDELAYCTRL primitive must be instantiated.
See IDELAYCTRL Usage and Design Guidelines
being used in VAR_LOAD mode are described in
C LD CE INC
0 x x x
1 1 x x
1 0 0 x
1 0 1 1
1 0 1 0
1 0 0 0
shows the IDELAY switching characteristics.
Symbol
IDELAYRESOLUTION
/T
ICECK ICKCE
/T
IINCCK ICKINC
/T
IRSTCK ICKRST
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TAP Setting
No Change
IDELAY_VALUE
No Change
Current Value +1
Current Value –1
No Change
for more details. The control pins
CNTVALUEIN CNTVALUEOUT
x No Change
CNTVALUEIN CNTVALUEIN
x No Change
x Current Value +1
x Current Value –1
0 No Change
IDELAY tap resolution
CE pin Setup/Hold with respect to C
INC pin Setup/Hold with respect to C
LD pin Setup/Hold with respect to C
Input Delay Resources (IDELAY)
IDELAYCTRL Usage and Design
Table 2-7.
TAP Setting
No Change
CNTVALUEIN
No Change
Current Value +1
Current Value –1
No Change
Description
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