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ISERDESE2 Primitive (ISERDESE2)
The ISERDESE2 primitive in 7 series devices (shown in
X-Ref Target - Figure 3-2
Table 3-1
Table 3-1: ISERDESE2 Port List and Definitions
Port Name
Type
Q1 – Q8
Output
O
Output
SHIFTOUT1
Output
SHIFTOUT2
Output
D
Input
DDLY
Input
7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
BITSLIP
CE1
CE2
CLK
CLKB
OCLK
OCLKB
CLKDIVP
CLKDIV
DYNCLKSEL
DYNCLKDIVSEL
SHIFTIN1
SHIFTIN2
RST
D
DDLY
OFB
Figure 3-2: ISERDESE2 Primitive
lists the available ports in the ISERDESE2 primitive.
Width
1 (each)
Registered outputs. See
1
Combinatorial output. See
1
Carry out for data width expansion. Connect to SHIFTIN1 of slave IOB. See
ISERDESE2 Width
1
Carry out for data width expansion. Connect to SHIFTIN2 of slave IOB. See
ISERDESE2 Width
1
Serial input data from IOB. See
1
Serial input data from IDELAYE2. See
DDLY.
www.xilinx.com
Input Serial-to-Parallel Logic Resources (ISERDESE2)
Figure
ISERDESE2
Primitive
Description
Registered Outputs – Q1 to
Combinatorial Output –
Expansion.
Expansion.
Serial Input Data from IOB -
Serial Input Data from IDELAYE2 -
3-2) is ISERDESE2.
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
SHIFTOUT1
SHIFTOUT2
O
UG471_c3_02_090810
Q8.
O.
D.
145
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