Stability After An Increment/Decrement Operation; Odelay Vhdl And Verilog Instantiation Template - Xilinx SelectIO 7 Series User Manual

Stability after an Increment/Decrement Operation

Figure 2-26
CE commands. Clearly, when the data value at tap 0 is different from the data value at tap
1, the output must change state. However, when the data values at tap 0 and tap 1 are the
same (e.g., both 0 or both 1), then the transition from tap 0 to tap 1 causes no glitch or
disruption on the output. This concept can be better comprehended by imagining the
transmitter data signal passing through the ODELAY tap chain. If tap 0 and tap 1 are both
near the center of the transmitted signal, the data at tap 0 will be no different than the data
at tap 1. In this case, the transition from tap 0 to tap 1 causes no change to the output. To
ensure that this is the case, the increment/decrement operation of ODELAY is designed to
be glitchless.
The user can therefore dynamically adjust the ODELAY tap setting in real-time while live
user data is passing through the ODELAYE2 primitive. The adjustments do not disrupt the
live user data as long as the current delay line value is near the centre of the transmitted
data signal.
The glitchless behavior also applies when an ODELAYE2 primitive is used in the path of a
clock signal. Adjusting the tap setting does not cause a glitch or disruption on the output.

ODELAY VHDL and Verilog Instantiation Template

VHDL and Verilog instantiation templates are available in the Libraries Guide for all
primitives and submodules.
In VHDL, each template has a component declaration section and an architecture section.
Each part of the template should be inserted within the VHDL design file. The port map of
the architecture section should include the design signals names.
7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
Output Delay Resources (ODELAY)—Not Available in HR Banks
shows the ODELAY line changing from tap 0 to tap 1 in response to INC and
www.xilinx.com 141
Send Feedback