Constraining The Core; Output Generation; Required Constraints; Clock Frequencies - Xilinx CAN FD v2.0 Product Manual

Table 4-1: Vivado IDE Parameter to User Parameter Relationship (Cont'd)
Vivado IDE Parameter/Value
Enable RX FIFO-1
Valid values are true and false.
RX FIFO-1 Depth
Valid values are 32 and 64.

Output Generation

For details, see the Vivado Design Suite User Guide: Designing with IP (UG896)

Constraining the Core

This section contains information about constraining the core in the Vivado Design Suite.

Required Constraints

CAN and AXI4 clocks are treated as asynchronous to each other and the core writes out
appropriate clock domain crossing constraints.
<project_name>/<project_name>.srcs/source_1/ip/<component_name>/
directory for core constraints.
Table 4-2: Core Constraint Files
<component_name>.xdc
Device, Package, and Speed Grade Selections
This section is not applicable for this IP core.

Clock Frequencies

The CAN clock and AXI4 clock can be asynchronous or clocked from the same source. When
both clocks are asynchronous to each other, the AXI4 clock is required to run at a higher
frequency.
• The CAN clock frequency can be 8 to 80 MHz.
• The AXI4 clock frequency can be 8 to 200 MHz.
CAN FD v2.0
PG223 December 5, 2018
User Parameter/Value
EN_RX_FIFO_1
Valid values are true and false.
C_RX_FIFO_1_DEPTH
Valid values are 32 and 64.
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Chapter 4: Design Flow Steps
true
This parameter is valid only
Note:
when the IP is in FIFO/Sequential
mode and RX FIFO-1 is enabled.
64
This parameter is valid only
Note:
when the IP is in FIFO/Sequential
mode and RX FIFO-1 is enabled.
Table 4-2 shows the files delivered in the
Description
Core constraints
Send Feedback
Default Value
[Ref 6].
83