Xilinx SelectIO 7 Series User Manual page 103

Table 1-56: DRIVE and SLEW Attributes, Bidirectional Buffers, and DCI Termination Type (Cont'd)
I/O Standard
MINI_LVDS_25
MOBILE_DDR
PCI33_3
PPDS_25
RSDS_25
SSTL135
SSTL135_R
SSTL135_DCI
SSTL135_T_DCI
SSTL15
SSTL15_R
SSTL15_DCI
SSTL15_T_DCI
SSTL18_I
SSTL18_I_DCI
SSTL18_II
SSTL18_II_DCI
SSTL18_II_T_DCI
TMDS_33
Notes:
1. The bidirectional buffers column describes the I/O standards use of a bidirectional signal. The standards labeled as required can
only be used with bidirectional signals and require primitives such as the IOBUF and IOBUFDS.
2. The DCI termination type column describes the type of termination available for the DCI I/O standards. Split refers to the
split-termination resistors.
3. Internal differential termination is always used in bidirectional configuration.
7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
DRIVE (mA)
I/O Bank
Availability
Outputs
HR N/A
HR N/A
HR N/A
HR N/A
HR N/A
Both N/A
HR N/A
HP N/A
HP N/A
Both N/A
HR N/A
HP N/A
HP N/A
Both N/A
HP N/A
Both N/A
HP N/A
HP N/A
HR N/A
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Rules for Combining I/O Standards in the Same Bank
SLEW
Bidirectional
Buffers
Outputs
(3)
N/A Yes
SLOW, FAST Yes
N/A Yes
N/A No
N/A No
SLOW, FAST Yes
SLOW, FAST Yes
SLOW, FAST No
SLOW, FAST Required
SLOW, FAST Yes
SLOW, FAST Yes
SLOW, FAST No
SLOW, FAST Required
SLOW, FAST No
SLOW, FAST No
SLOW, FAST Yes
SLOW, FAST Yes
SLOW, FAST Required
N/A No
(2)
DCI Type
(1)
Outputs Inputs
None None
None None
None None
None None
None None
None None
None None
None Split
None Split
None None
None None
None Split
None Split
None None
None Split
None None
Split Split
None Split
None None
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