Xilinx SelectIO 7 Series User Manual page 136

Chapter 2: SelectIO Logic Resources
Pipeline Register Load - LDPIPEEN
When High, this input loads the pipeline register with the value currently on the
CNTVALUEIN pins.
Pipeline Register Reset - REGRST
When high, this input resets the pipeline register to all zeroes.
C Pin Polarity Switch - CINVCTRL
The CINVCTRL pin is used for dynamically switching the polarity of C pin. This is for use
in applications when glitches are not an issue. When switching the polarity, do not use
ODELAY control pins for two clock cycles.
Count Value In - CNTVALUEIN
The CNTVALUEIN pins are used together with the LD pin for dynamically switching the
loadable tap value.
Count Value Out - CNTVALUEOUT
The CNTVALUEOUT pins are used for reporting the loaded tap value.
Increment/Decrement Signals - CE, INC
The increment/decrement is controlled by the enable signal (CE). This interface is only
available when ODELAY is in VARIABLE, VAR_LOAD, or VAR_LOAD_PIPE mode.
As long as CE remains High, ODELAY will increment or decrement by
T
will increment or decrement; INC = 1 increments, INC = 0 decrements, synchronously to
the clock (C). If CE is Low the delay through ODELAY will not change regardless of the
state of INC.
When CE goes High, the increment/decrement operation begins on the next positive clock
cycle. When CE goes Low, the increment/decrement operation ceases on the next positive
clock edge.
The programmable delay taps in the ODELAYE2 primitive wrap-around. When the end of
the delay tap is reached (tap 31) a subsequent increment function will return to tap 0. The
same applies to the decrement function: decrementing below zero moves to tap 31.
The pipeline register functionality in VAR_LOAD_PIPE mode is extremely useful in bus
structure designs. Individual delays might be (pipeline) loaded one at a time using
LDPIPEEN and then all delays updated to their new values at the same time using the LD
pin.
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every clock (C) cycle. The state of INC determines whether ODELAY
IDELAYRESOLUTION
www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018