Hstl_ Ii_Dci And Hstl_ Ii_Dci_18; Hstl_ Ii_T_Dci And Hstl_ Ii_T_Dci_18; Diff_Hstl_I And Diff_Hstl_I_18; Diff_Hstl_I_Dci And Diff_Hstl_I_Dci_18 - Xilinx SelectIO 7 Series User Manual

HSTL_ II_DCI and HSTL_ II_DCI_18

Table 1-23: Available I/O Bank Type
HSTL_II_DCI and HSTL_II_DCI_18 provide on-chip split thevenin termination powered
from V
use in bidirectional links.

HSTL_ II_T_DCI and HSTL_ II_T_DCI_18

Table 1-24: Available I/O Bank Type
HSTL_ II_T_DCI and HSTL_ II_T_DCI_18 provide on-chip split-thevenin termination
powered from V
receiver when the driver is 3-stated. When the driver is not 3-stated, these two standards
do not have termination.

DIFF_HSTL_I and DIFF_HSTL_I_18

Table 1-25: Available I/O Bank Type
Differential HSTL class-I pairs complementary single-ended HSTL_I type drivers with a
differential receiver, and are intended to be used in unidirectional links.

DIFF_HSTL_I_DCI and DIFF_HSTL_I_DCI_18

Table 1-26: Available I/O Bank Type
Differential HSTL class-I pairs complementary single-ended HSTL_I type drivers with a
differential receiver, including on-chip split-thevenin termination, and are intended to be
used in unidirectional links.

DIFF_HSTL_ II and DIFF_HSTL_II_18

Table 1-27: Available I/O Bank Type
Differential HSTL class-II pairs complementary single-ended HSTL_II type drivers with a
differential receiver. Differential HSTL class-II is intended to be used in bidirectional links.
7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
HR HP
N/A Available
, creating an equivalent termination voltage of V
CCO
HR HP
N/A Available
that creates an equivalent termination voltage of V
CCO
HR HP
Available Available
HR HP
N/A Available
HR HP
Available Available
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Supported I/O Standards and Terminations
/2, and are intended for
CCO
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/2 at the
CCO
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