Idelay Ports - Xilinx SelectIO 7 Series User Manual

IDELAY Ports

Data Input from the IOB - IDATAIN
The IDATAIN input is driven by its associated IOB. IDELAY can drive data to either an
ILOGICE2/ISERDESE2 or ILOGICE3/ISERDESE2 block, directly into the FPGA logic, or
to both through the DATAOUT port with a delay set by the IDELAY_VALUE.
Data Input from the FPGA Logic - DATAIN
The DATAIN input is directly driven by the FPGA logic providing a logic accessible delay
line. The data is driven back into the FPGA logic through the DATAOUT port with a delay
set by the IDELAY_VALUE. DATAIN can be locally inverted. The data cannot be driven to
an IOB.
Data Output - DATAOUT
Delayed data from the two data input ports. DATAOUT can drive to either an ILOGICE2/
ISERDESE2 or ILOGICE3/ISERDESE2 block, directly into the FPGA logic, or to both.
Clock Input - C
All control inputs to IDELAYE2 primitive (REGRST, LD, CE, and INC) are synchronous to
the clock input (C). A clock must be connected to this port when IDELAY is configured in
VARIABLE, VAR_LOAD, or VAR_LOAD_PIPE mode. C can be locally inverted, and must
be supplied by a global or regional clock buffer. If the ODELAYE2 primitive is used in the
same I/O bank as the IDELAYE2 primitive, C must use the same clock net for both
primitives.
Module Load - LD
When in VARIABLE mode, the IDELAY load port, LD, loads the value set by the
IDELAY_VALUE attribute. The default value of the IDELAY_VALUE attribute is zero.
When the default value is used, the LD port acts as an asynchronous reset for the ILDELAY.
The LD signal is an active-High signal and is synchronous to the input clock signal (C).
When in VAR_LOAD mode, the IDELAY load port, LD, loads the value set by the
CNTVALUEIN. The value present at CNTVALUEIN[4:0] will be the new tap value. When
in VAR_LOAD_PIPE mode, the IDELAY load port LD loads the value currently in the
pipeline register. The value present in the pipeline register will be the new tap value.
C Pin Polarity Switch - CINVCTRL
The CINVCTRL pin is used for dynamically switching the polarity of the C pin. This is for
use in applications when glitches are not an issue. When switching the polarity, do not use
IDELAY control pins for two clock cycles.
Count Value In - CNTVALUEIN
The CNTVALUEIN pins are used for dynamically switching the loadable tap value.
Count Value Out - CNTVALUEOUT
The CNTVALUEOUT pins are used for reporting the loaded tap value.
Pipeline Register Load - LDPIPEEN
When High, this input loads the pipeline register with the value currently on the
CNTVALUEIN pins.
7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
www.xilinx.com
Input Delay Resources (IDELAY)
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