Xilinx SelectIO 7 Series User Manual page 89

Table 1-40: IOSTANDARD Attributes for Single-Ended HSTL, SSTL, HSUL, or MOBILE_DDR I/O Standards
Attributes IBUF, IBUFG, OBUF, or OBUFT
HP I/O Banks
HSTL_I
HSTL_I_12
HSTL_I_18
HSTL_I_DCI
HSTL_I_DCI_18
HSTL_II
HSTL_II_18
HSTL_II_DCI
HSTL_II_DCI_18
N/A
N/A
SSTL12
SSTL12_DCI
N/A
N/A
IOSTANDARD
SSTL135
SSTL135_DCI
N/A
N/A
SSTL15
SSTL15_DCI
N/A
SSTL18_I
SSTL18_I_DCI
SSTL18_II
SSTL18_II_DCI
N/A
HSUL_12
HSUL_12_DCI
N/A
7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
Primitives
HR I/O Banks
HSTL_I N/A
N/A N/A
HSTL_I_18 N/A
N/A N/A
N/A N/A
HSTL_II HSTL_II
HSTL_II_18 HSTL_II_18
N/A HSTL_II_DCI
N/A HSTL_II_DCI_18
N/A HSTL_II_T_DCI
N/A HSTL_II_T_DCI_18
N/A SSTL12
N/A N/A
N/A SSTL12_T_DCI
SSTL135_R N/A
SSTL135 SSTL135
N/A N/A
N/A SSTL135_T_DCI
SSTL15_R N/A
SSTL15 SSTL15
N/A N/A
N/A SSTL15_T_DCI
SSTL18_I N/A
N/A N/A
SSTL18_II SSTL18_II
N/A SSTL18_II_DCI
N/A SSTL18_II_T_DCI
HSUL_12 HSUL_12
N/A HSUL_12_DCI
MOBILE_DDR N/A
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Supported I/O Standards and Terminations
IOBUF
HP I/O Banks
N/A
N/A
N/A
N/A
N/A
HSTL_II
HSTL_II_18
N/A
N/A
N/A
N/A
N/A
N/A
N/A
SSTL135_R
SSTL135
N/A
N/A
SSTL15_R
SSTL15
N/A
N/A
N/A
N/A
SSTL18_II
N/A
N/A
HSUL_12
N/A
MOBILE_DDR
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HR I/O Banks
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