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Figure 1-54
HSTL class-II (1.5V or 1.8V) with bidirectional DCI termination. In a specific circuit, all
drivers and receivers must be at the same voltage level (either 1.5V or 1.8V); they are not
interchangeable. Only HP I/O banks support the DCI standards. The internal
split-termination resistors are always present, independent of whether the drivers are
3-stated.
X-Ref Target - Figure 1-54
DCI
DIFF_HSTL_II_DCI
DIFF_HSTL_II_DCI_18
R
VRN
R
VRP
DIFF_HSTL_II_DCI
DIFF_HSTL_II_DCI_18
V
CCO
for DIFF_HSTL_II_DCI
V
DIFF_HSTL_II_DCI
CCO
for DIFF_HSTL_II_DCI_18
DIFF_HSTL_II_DCI_18
+
R
VRN
–
R
VRP
Figure 1-54: Differential HSTL Class II (1.5V or 1.8V) DCI Bidirectional Termination
7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
shows a sample circuit illustrating a termination technique for differential
IOB
V
= 1.5V
CCO
for DIFF_HSTL_II_DCI
V
= 1.8V
CCO
for DIFF_HSTL_II_DCI_18
= 2Z 0 = 100Ω
= 2Z 0 = 100Ω
= 1.5V
= 1.8V
= 2Z 0 = 100Ω
= 2Z 0 = 100Ω
www.xilinx.com
Supported I/O Standards and Terminations
IOB
V
= 1.5V
CCO
for DIFF_HSTL_II_DCI
V
= 1.8V
CCO
for DIFF_HSTL_II_DCI_18
R
= 2Z 0 = 100Ω
VRN
Z 0
R
= 2Z 0 = 100Ω
VRP
Z 0
V
= 1.5V
CCO
+
for DIFF_HSTL_II_DCI
V
= 1.8V
CCO
for DIFF_HSTL_II_DCI_18
R
= 2Z 0 = 100Ω
VRN
R
= 2Z 0 = 100Ω
VRP
DIFF_HSTL_II_DCI
DIFF_HSTL_II_DCI_18
DIFF_HSTL_II_DCI
DIFF_HSTL_II_DCI_18
DIFF_HSTL_II_DCI
DIFF_HSTL_II_DCI_18
+
–
ug471_c1_44_121214
71
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