State Of I/Os During And After Configuration; Series Fpga Dci-Only Available In The Hp I/O Banks; Introduction - Xilinx SelectIO 7 Series User Manual

There is a design constraint for I/O nets and primitives called VCCAUX_IO, which should
be specified in the design if the V
7 Series FPGA SelectIO Attributes/Constraints, page 46
The V
packages in groups of three or four HP I/O banks. The package files chapter of
UG475: 7 Series FPGA Packaging and Pinout Specification contains links to the ASCII package
files, and the figures in the device diagrams chapter indicate which device/package
combinations contain HP I/O banks with V
indicate which bank's V
V
internal group number. The package files contain a column called "VCCAUX Group" that
shows for every I/O pin which V
pins that are in the same V
nets or primitives that are compatible. All V
should be tied to the same voltage rail on the board. FBG packages for Kintex-7 devices
contain V
are powered from the main V

State of I/Os During and After Configuration

7 series FPGAs have pins dedicated to configuration functions contained in I/O bank 0.
Banks 14 and 15 also contain I/O pins known as multi-function or multi-purpose pins that
can also be used for configuration, but then convert to normal I/O pins after configuration
is complete. Additionally in SSI devices, pins in banks 11, 12, 17, 18, 20, and 21 have
restrictions during configuration similar to multi-function pins. However, pins in these
banks do not have any configuration functions.
In devices where bank 14 and/or bank 15 are HR banks and configured with a V
requirement < 1.8V, inputs might have a 0-1-0 transition to the interconnect logic during
configuration if the input is tied to 0 or floating and the configuration voltage is > 2.5V. For
further details, refer to UG470: 7 Series FPGAs Configuration User Guide.
7 Series FPGA DCI—Only available in the HP I/O banks

Introduction

As FPGAs get bigger and system clock speeds get faster, PC board design and
manufacturing becomes more difficult. With ever faster edge rates, maintaining signal
integrity becomes a critical issue. PC board traces must be properly terminated to avoid
reflections or ringing.
To terminate a trace, resistors are traditionally added to make the output and/or input
match the impedance of the receiver or driver to the impedance of the trace. However, due
to increased device I/Os, adding resistors close to the device pins increases the board area
and component count, and can in some cases be physically impossible. To address these
issues and to achieve better signal integrity, Xilinx developed the digitally controlled
impedance (DCI) technology.
Depending on the I/O standard, DCI can either control the output impedance of a driver,
or add a parallel termination present at the driver and/or receiver, with the goal of
accurately matching the characteristic impedance of the transmission line. DCI actively
adjusts these impedances inside the I/O to calibrate to external precision reference
resistors placed on the VRN and VRP pins. This compensates for changes in I/O
7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
pins are connected together internally inside Kintex-7 and Virtex-7 device
CCAUX_IO
CCAUX_IO
package pin names have the syntax VCCAUX_IO_G#, where the # is the
CCAUX_IO
CCAUX_IO
pins but are no connects internally. All HP I/O banks in those packages
CCAUX_IO
www.xilinx.com
7 Series FPGA DCI—Only available in the HP I/O banks
pins for any banks are to be set at 2.0V. See
CCAUX_IO
pins. The ASCII package files
CCAUX_IO
pins are grouped together inside the package. The
group that I/O bank is associated with. All I/O
CCAUX
group must have VCCAUX_IO constraints on their
pins that are grouped together
CCAUX_IO
rail instead.
CCAUX
for information on this constraint.
CCO
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