Same_Edge Mode; Same_Edge_Pipelined Mode - Xilinx SelectIO 7 Series User Manual

Chapter 2: SelectIO Logic Resources
X-Ref Target - Figure 2-5
C
CE
D0A D1A D2A
D
Q1 D0A
Q2

SAME_EDGE Mode

In the SAME_EDGE mode, the data is presented into the FPGA logic on the same clock
edge. This structure is similar to the Virtex-6 FPGA implementation.
Figure 2-6
timing diagram, the output pairs Q1 and Q2 are no longer (0) and (1). Instead, the first pair
presented is pair Q1 (0) and Q2 (don't care), followed by pair (1) and (2) on the next clock
cycle.
X-Ref Target - Figure 2-6
C
CE
D0A D1A
D
Q1 D0A
Don't care
Q2

SAME_EDGE_PIPELINED Mode

In the SAME_EDGE_PIPELINED mode, the data is presented into the FPGA logic on the
same clock edge.
Unlike the SAME_EDGE mode, the data pair is not separated by one clock cycle. However,
an additional clock latency is required to remove the separated effect of the SAME_EDGE
mode.
SAME_EDGE_PIPELINED mode. The output pairs Q1 and Q2 are presented to the FPGA
logic at the same time.
110
Send Feedback
D3A D4A D5A D6A D7A D8A D9A D10A D11A D12A D13A
D2A D4A
D1A D3A
Figure 2-5: Input DDR Timing in OPPOSITE_EDGE Mode
shows the timing diagram of the input DDR using SAME_EDGE mode. In the
D2A D3A D4A D5A
D2A D4A
D1A D3A
Figure 2-6: Input DDR Timing in SAME_EDGE Mode
Figure 2-7 shows the timing diagram of the input DDR using the
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D6A D8A
D5A D7A
D6A D7A D8A D9A D10A
D6A D8A
D5A D7A
7 Series FPGAs SelectIO Resources User Guide
D10A D12A
D9A D11A
ug471_c2_03_090810
D11A
D10A
D9A D11A
ug471_c2_04_090810
UG471 (v1.10) May 8, 2018