Xilinx SelectIO 7 Series User Manual page 114

Chapter 2: SelectIO Logic Resources
X-Ref Target - Figure 2-10
(Reset)
Clock Event 1
•
•
Clock Event 4
•
Clock Event 9
•
Table 2-3
7 series FPGA data sheets.
Table 2-3: ILOGIC Switching Characteristics
Setup/Hold
T
T
T
114
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1 2
CLK
T
T
IDOCK
IDOCK
D
T
ICE1CK
CE1
S/R
T
ICKQ
Q1
Q2
Figure 2-10: ILOGIC in IDDR Mode Timing Characteristics
At time T before Clock Event 1, the input clock enable signal becomes
ICE1CK
valid-high at the CE1 input of both of the DDR input registers, enabling them for
incoming data. Since the CE1 and D signals are common to both DDR registers, care
must be taken to toggle these signals between the rising edges and falling edges of
CLK as well as meeting the register setup-time relative to both edges.
At time T before Clock Event 1 (rising edge of CLK), the input signal becomes
IDOCK
valid-high at the D input of both registers and is reflected on the Q1 output of
input-register 1 at time T
At time T before Clock Event 4 (falling edge of CLK), the input signal becomes
IDOCK
valid-low at the D input of both registers and is reflected on the Q2 output of
input-register 2 at time T
At time T before Clock Event 9, the S/R signal (configured as synchronous reset
ISRCK
in this case) becomes valid-high resetting Q1 at time T
Q2 at time T after Clock Event 10.
ICKQ
describes the timing parameters of the ILOGIC switching characteristics in the
Symbol
/T CE1 pin Setup/Hold with respect to CLK
ICE1CK ICKCE1
/T S/R pin Setup/Hold with respect to CLK
ISRCK ICKSR
/T D pin Setup/Hold with respect to CLK
IDOCK IOCKD
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3 4 5 6
T
ICKQ
(OPPOSITE_EDGE Mode)
after Clock Event 1.
ICKQ
after Clock Event 4 (no change in this case).
ICKQ
Description
7 Series FPGAs SelectIO Resources User Guide
7 8 9 10
T
ISRCK
T
ICKQ
UG471_c2_08_081215
after Clock Event 9, and
ICKQ
UG471 (v1.10) May 8, 2018
11
T
ICKQ