Table of Contents
Advertisement
Chapter 2:
SelectIO Logic Resources
allows the tap value to be dynamically set. When in VAR_LOAD_PIPE mode, the LD pin
enables the current value in the pipeline register to be loaded into the output delay.
ODELAY_VALUE Attribute
The ODELAY_VALUE attribute specifies tap delays. The possible values are any integer
from 0 to 31. The default value is zero. The value of the tap delay reverts to
ODELAY_VALUE when the tap delay is reset by asserting the LD signal. In VAR_LOAD or
VAR_LOAD_PIPE mode, this attribute is assumed to be zero.
HIGH_PERFORMANCE_MODE Attribute
When TRUE, this attribute reduces the output jitter. This reduction in jitter results in a
slight increase in power dissipation from the ODELAYE2 primitive.
SIGNAL_PATTERN Attribute
Clock and data signals have different electrical profiles and therefore accumulate different
amounts of jitter in the ODELAY chain. By setting the SIGNAL_PATTERN attribute, the
user enables timing analyzer to account for jitter appropriately when calculating timing. A
clock signal is periodic in nature and does not have long sequences of consecutive ones or
zeroes, while data is random in nature and can have long and short sequences of ones and
zeroes.
ODELAY Modes
When used as ODELAY, the data input comes from either IBUF or the FPGA logic and the
output goes to ILOGICE2/ISERDESE2 or ILOGICE3/ISERDESE2. There are four modes of
operation available:
•
•
Table 2-15: Control Pin when ODELAY_TYPE = VARIABLE
138
Send Feedback
Fixed delay mode (ODELAY_TYPE = FIXED)
In the fixed delay mode, the delay value is preset at configuration to the tap number
determined by the attribute ODELAY_VALUE. Once configured, this value cannot be
changed. When used in this mode, the IDELAYCTRL primitive must be instantiated.
See
IDELAYCTRL Usage and Design Guidelines
Variable delay mode (ODELAY_TYPE = VARIABLE)
In the variable delay mode, the delay value can be changed after configuration by
manipulating the control signals CE and INC. When used in this mode, the
IDELAYCTRL primitive must be instantiated. See
Guidelines
for more details. The control pins being used in VARIABLE mode are
described in
Table
2-6.
C
LD
CE
INC
0
x
x
x
No Change
1
1
x
x
ODELAY_VALUE
1
0
0
x
No Change
1
0
1
1
Current Value +1
1
0
1
0
Current Value –1
1
0
0
0
No Change
www.xilinx.com
for more details.
IDELAYCTRL Usage and Design
TAP Setting
7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
Advertisement
Table of Contents
