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Chapter 1:
SelectIO Resources
Simultaneous Switching Outputs
Due to package inductance, each part/package supports a limited number of
simultaneous switching outputs (SSOs), particularly when using fast, high-drive outputs.
Fast, high-drive outputs should only be used when required by the application.
The SSN predictor tool within the PlanAhead software provides a way of analyzing the
amount of noise margin on each I/O pin in a design based on information for the pin (the
victim), as well as all other pins (aggressors) in the design. The tool takes into account I/O
pin locations, I/O standards, slew rates, and terminations used, and provides a value for
the noise margin for each pin based on these characteristics. The noise margin does not
include any system-level characteristics such as board trace cross-talk or reflections due to
board impedance discontinuities.
Ground or power bounce occurs when a large number of outputs simultaneously switch in
the same direction. The output drive transistors all conduct current to a common rail.
Low-to-High transitions connect to the V
to the ground rail. The resulting cumulative current transient induces a voltage difference
across the inductance that exists between the internal and external ground levels, or
internal and external V
package lead frame, die routing, package routing, and ball inductance. Any SSO-induced
voltage consequently affects internal switching noise margins and ultimately signal
quality.
The SSN predictor results assume that the FPGA is soldered on the PCB and that the board
uses sound design practices. The noise margin values do not apply for FPGAs mounted in
sockets due to the additional BGA ball inductance introduced by the socket.
Pin Planning to Mitigate SSO Sensitivity
When performing pin planning of a design, it is important to choose I/O pin placements
that separate strong outputs and/or SSOs from sensitive inputs and outputs (particularly
asynchronous inputs). Strong outputs tend to be the class-II versions of HSTL and SSTL
drivers, PCI variants, and any LVCMOS or LVTTL with drive strengths over 8 mA.
Sensitive inputs and outputs can have a low noise margin and tend to be high-speed
signals or signals where the swing is reduced by parallel receiver termination. Because
localized SSO noise in 7 series FPGAs is based on the proximity of signals to one another,
it is important to try to separate signals based on the position of the package solder balls.
To further reduce potential noise induced from SSOs, outputs should be distributed evenly
rather than clustered in one area. SSOs within a bank should be spread across the bank as
much as possible. Whenever possible, SSOs should be distributed into multiple banks.
The floorplanning capability in the Vivado® Design Suite and the PlanAhead tool in the
ISE software can help accomplish pin planning to avoid SSO sensitivity issues. By clicking
on a package pin in the Package window, a corresponding IOB is highlighted in the Device
window. These IOB site types represent the die pads and show the relative physical
location around the die edge. Through the use of the PlanAhead tool and the floorplanning
capability in the Vivado Design Suite, intelligent pin placement can be used to separate the
die pads of pins. This is implemented by separating the die pads of pins with strong
outputs and SSOs from the die pads of pins with sensitive inputs and outputs. SSO effects
can also be minimized by adding virtual ground pins and virtual V
ground is created by defining an output pin driven by a logic 0 at the highest drive strength
available and connected to ground on the board. Similarly, a virtual V
defining an output pin driven by a logic 1 at the highest drive strength and connected to
V
104
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CCO
on the board.
CCO
www.xilinx.com
rail, while High-to-Low transitions connect
CCO
levels. The inductance is associated with bonding wires,
7 Series FPGAs SelectIO Resources User Guide
pins. A virtual
CCO
pin is created by
CCO
UG471 (v1.10) May 8, 2018
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