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Chapter 1:
SelectIO Resources
SSTL18, SSTL15, SSTL135, SSTL12
Figure 1-57
SSTL18, SSTL15, SSTL135, or SSTL12. In a specific circuit, all drivers and receivers must be
at the same voltage level (1.8V, 1.5V, 1.35V, or 1.2V); they are not interchangeable. Also
shown in
in an output pin.
X-Ref Target - Figure 1-57
External Termination
SSTL18_(I/II)
SSTL15(_R)
SSTL135(_R)
SSTL12
DCI
V
1.8V for SSTL18_II_DCI
SSTL18_(I/II)_DCI
SSTL15_DCI
SSTL135_DCI
R
= 2Z 0 = 100Ω
VRN
SSTL12_DCI
R
= 2Z 0 = 100Ω
VRP
Figure 1-57: SSTL18, SSTL15, SSTL135, or SSTL12 Unidirectional Termination
78
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shows a sample circuit illustrating a unidirectional termination technique for
Figure
1-57, only SSTL18_II_DCI has internal split-termination resistors present
IOB
V
=
TT
0.9V for SSTL18_II
R P = Z 0 = 50Ω
Z 0
IOB
=
CCO
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V
=
TT
0.9V for SSTL18_(I/II)
0.75V for SSTL15(_R)
IOB
0.675V for SSTL135(_R)
0.6V for SSTL12
R P = Z 0 = 50Ω
V
0.9V for SSTL18_(I/II)
0.75V for SSTL15(_R)
0.675V for SSTL135(_R)
0.6V for SSTL12
IOB
V
=
CCO
1.8V for SSTL18_(I/II)_DCI
1.5V for SSTL15_DCI
1.35V for SSTL135_DCI
1.2V for SSTL12_DCI
R
= 2Z 0 = 100Ω
VRN
Z 0
R
= 2Z 0 = 100Ω
VRP
7 Series FPGAs SelectIO Resources User Guide
SSTL18_(I/II)
SSTL15(_R)
SSTL135(_R)
SSTL12
+
=
–
REF
SSTL18_(I/II)_DCI
SSTL15_DCI
SSTL135_DCI
SSTL12_DCI
+
–
V
=
REF
0.9V for SSTL18_(I/II)_DCI
0.75V for SSTL15_DCI
0.675V for SSTL135_DCI
0.6V for SSTL12_DCI
ug471_c1_47_121214
UG471 (v1.10) May 8, 2018
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