Stability After An Increment/Decrement Operation; Idelay Vhdl And Verilog Instantiation Template - Xilinx SelectIO 7 Series User Manual

Clock Event 0
Before LD is pulsed the tap setting and therefore CNTVALUEOUT are at an unknown
value.
Clock Event 1
On the rising edge of C, LD is detected as High causing the output DATAOUT to have a
delay defined by the CNTINVALUE, and changing the tap setting to tap 2. The
CNTVALUEOUT is updated to represent the new tap value.
Clock Event 2
A pulse on CE and INC are captured on the rising edge of C. This indicates an increment
operation. The output changes without glitches from tap 2 to tap 3. The CNTVALUEOUT
is updated to represent the new tap value.
Clock Event 3
On the rising edge of C, a LD is detected as High causing the output DATAOUT to be
delayed by the CNTINVALUE. The CNTVALUEOUT shows the value of the tap setting.
The output will remain at tap 10 indefinitely until there is further activity on the LD, CE, or
INC pins.

Stability after an Increment/Decrement Operation

Figure 2-12
command. Clearly, when the data value at tap 0 is different from the data value at tap 1, the
output must change state. However, when the data values at tap 0 and tap 1 are the same
(e.g., both 0 or both 1), then the transition from tap 0 to tap 1 causes no glitch or disruption
on the output. This concept can be better comprehended by imagining the receiver data
signal passing through the IDELAY tap chain. If tap 0 and tap 1 are both near the center of
the receiver data eye, then the data sampled at tap 0 will be no different than the data
sampled at tap 1. In this case, the transition from tap 0 to tap 1 causes no change to the
output. To ensure that this is the case, the increment/decrement operation of IDELAY is
designed to be glitchless. The same explanation also applies to the VAR_LOAD behavior
shown in
delay by more than one tap, which could potentially result in a sample point that is well
away from the current eye centre point.
The user can therefore dynamically adjust the IDELAY tap setting in real-time while live
user data is passing through the IDELAYE2 primitive. The adjustments do not disrupt the
live user data, provided that the current delay line value is near the middle of the received
data eye.
The glitchless behavior also applies when an IDELAYE2 primitive is used in the path of a
clock signal. Adjusting the tap setting does not cause a glitch or disruption on the output,
provided that the delay line value is not near the edges seen in the received clock signal. In
this case, the tap setting of the IDELAYE2 primitive in the clock path can be adjusted
without disrupting any clock management elements or state machines that could be
running on that clock.

IDELAY VHDL and Verilog Instantiation Template

VHDL and Verilog instantiation templates are available in the Libraries Guide for all
primitives and submodules.
7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
shows the delay line changing from tap 0 to tap 1 in response to an INC and CE
Figure 2-13. VAR_LOAD does, however, give the possibility of changing the
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Input Delay Resources (IDELAY)
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