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Figure 1-60
SSTL18, SSTL15, SSTL135, or SSTL12 with unidirectional DCI termination. In a specific
circuit, all drivers and receivers must be at the same voltage level (1.8V, 1.5V, 1.35V, or
1.2V); they are not interchangeable. Also shown in
internal split-termination resistors present in an output pin.
X-Ref Target - Figure 1-60
DCI
V
DIFF_SSTL18_(I/II)_DCI
CCO
DIFF_SSTL15_DCI
1.8V for DIFF_SSTL18_II_DCI
DIFF_SSTL135_DCI
DIFF_SSTL12_DCI
DIFF_SSTL18_(I/II)_DCI
V
CCO
DIFF_SSTL15_DCI
1.8V for DIFF_SSTL18_II_DCI
DIFF_SSTL135_DCI
DIFF_SSTL12_DCI
Figure 1-60: Differential SSTL18, SSTL15, SSTL135, or SSTL12 Unidirectional DCI Termination
7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
shows a sample circuit illustrating a termination technique for differential
IOB
=
R
= 2Z 0 = 100Ω
VRN
R
= 2Z 0 = 100Ω
VRP
=
R
= 2Z 0 = 100Ω
VRN
R
= 2Z 0 = 100Ω
VRP
www.xilinx.com
Supported I/O Standards and Terminations
Figure
1-60, only SSTL18_II_DCI has
IOB
V
=
CCO
1.8V for DIFF_SSTL18_(I/II)_DCI
1.5V for DIFF_SSTL15_DCI
1.35V for DIFF_SSTL135_DCI
1.2V for DIFF_SSTL12_DCI
R
= 2Z 0 = 100Ω
VRN
Z 0
R
= 2Z 0 = 100Ω
VRP
V
=
CCO
1.8V for DIFF_SSTL18_(I/II)_DCI
1.5V for DIFF_SSTL15_DCI
1.35V for DIFF_SSTL135_DCI
1.2V for DIFF_SSTL12_DCI
R
= 2Z 0 = 100Ω
VRN
Z 0
R
= 2Z 0 = 100Ω
VRP
DIFF_SSTL18_(I/II)_DCI
DIFF_SSTL15_DCI
DIFF_SSTL135_DCI
DIFF_SSTL12_DCI
+
–
ug471_c1_50_121214
81
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