Revision History - Xilinx SelectIO 7 Series User Manual

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Revision History

The following table shows the revision history for this document.
Date Version
03/01/2011 1.0
04/06/2011 1.0.1
05/31/2011 1.1
07/20/2012 1.2
7 Series FPGAs SelectIO Resources User Guide
Initial Xilinx release.
Updated disclaimer and copyright sections on
Added New Features. Updated the example device including
partgen example on page 24. Added
Guidelines.
Updated the BITSLIP Submodule
Bits from Data Input Stream (D) of Figure 3-12.
Updated paragraph before
V and V . Updated
CCO CCAUX_IO
Configuration Option, DCIUpdateMode Configuration
and Special DCI Requirements for Some
cascading guidelines after
Uncalibrated Split Termination in High-Range I/O Banks
FPGA SelectIO Primitives. Added
Constraint. Updated IBUF_LOW_PWR
Drive Strength Attributes,
OBUFT, and IOBUF, and 7 Series FPGA I/O Resource VHDL/Verilog
Internal V inside Differential Termination Attribute, page
REF
attribute in Table 1-10. Updated titles of
and LVDS_25 (Low Voltage Differential
Added IN_TERM attribute to
Table 1-55. Added Simultaneous Switching
www.xilinx.com
Revision
page 2.
VRN/VRP External Resistance Design Migration
section including Figure
Table 1-1. Added LVDS signaling to
Xilinx DCI. Removed V
Banks. Updated
Figure 1-7. Updated table note in
DCI_CASCADE Constraint
Attribute, Output Slew Rate
PULLUP/PULLDOWN/KEEPER Attribute for IBUF,
Figure 1-41 through
Signaling), including adding
SSTL (Stub-Series Terminated
Outputs.
Figure 1-15 and the
3-12. Removed Figure 3-13:
Table 1-1. Updated
. Added Match_cycle
CCINT
Option, DCIRESET Primitive,
DCI Cascading. Updated DCI
Table 1-3. Added
(IN_TERM). Updated 7 Series
and VCCAUX_IO
Attributes, Output
Examples. Put
49. Updated DRIVE
Figure 1-44. Updated LVDS
Figure 1-72.
Logic). Added table note to
UG471 (v1.10) May 8, 2018