Xilinx SelectIO 7 Series User Manual page 144

Chapter 3: Advanced SelectIO Logic Resources
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Figure 3-1
components and features of the block including the optional inverters.
X-Ref Target - Figure 3-1
OFB
DDLY
D
CE1
CE2
DYNCLKSEL
CLKB
CLK
OCLK
DYNCLKDIVSEL
CLKDIV
CLKDIVP
RST
BITSLIP
144
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ISERDESE2 contains dedicated circuitry (including the OCLK input pin) to handle the
strobe-to-FPGA clock domain crossover entirely within the ISERDESE2 block. This
allows for higher performance and a simplified implementation.
Dedicated support for networking interfaces
Dedicated support for DDR3 interfaces
Dedicated support for QDR interfaces
Dedicated support for asynchronous interfaces
shows the block diagram of the ISERDESE2, highlighting all the major
IOB
Multiplexers
CE
Module
Figure 3-1: ISERDESE2 Block Diagram
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Serial-to-
Parallel
Converter
7 Series FPGAs SelectIO Resources User Guide
O
SHIFTIN1/2
SHIFTOUT1/2
Q1:Q8
Bitslip
Module
UG471_c3_01_080210
UG471 (v1.10) May 8, 2018