Split-Termination Dci (Thevenin Equivalent Termination To Vcco/2) - Xilinx SelectIO 7 Series User Manual

Chapter 1: SelectIO Resources
Split-Termination DCI (Thevenin Equivalent Termination to V
Some I/O standards (e.g., HSTL and SSTL) require an input termination resistance (R) to a
V
X-Ref Target - Figure 1-10
Split-termination DCI creates a Thevenin equivalent circuit using two resistors of twice the
resistance value (2R). One terminates to V
provides an equivalent termination to V
resistance is set by the external reference resistors. For example, to achieve the Thevenin
equivalent parallel-termination circuit of 50Ω to V
precision resistors at the VRN and VRP pins. The DCI input standards supporting split
termination are shown in
Table 1-2: All DCI I/O Standards Supporting Split-Termination DCI
HSTL_I_DCI
HSTL_I_DCI_18
HSTL_II_DCI
HSTL_II_DCI_18
HSTL_II_T_DCI
HSTL_II_T_DCI_18
26
Send Feedback
voltage of V /2 (see
TT CCO
Z
Figure 1-10: Input Termination to V
Table
DIFF_HSTL_I_DCI
DIFF_HSTL_I_DCI_18
DIFF_HSTL_II_DCI
DIFF_HSTL_II_DCI_18
DIFF_HSTL_II_T_DCI
DIFF_HSTL_II_T_DCI_18
www.xilinx.com
Figure 1-10).
V /2
CCO
IOB
R
0
V
REF
7 Series FPGA
, the other to ground. Split-termination DCI
CCO
/2 using this method. The 2R termination
CCO
CCO
1-2.
SSTL18_I_DCI
SSTL18_II_DCI
SSTL18_II_T_DCI
SSTL15_DCI
SSTL15_T_DCI
SSTL135_DCI
SSTL135_T_DCI
SSTL12_DCI
SSTL12_T_DCI
7 Series FPGAs SelectIO Resources User Guide
/2)
CCO
UG471_c1_12_011811
/2 without DCI
CCO
/2, would require 100Ω external
DIFF_SSTL18_I_DCI
DIFF_SSTL18_II_DCI
DIFF_SSTL18_II_T_DCI
DIFF_SSTL15_DCI
DIFF_SSTL15_T_DCI
DIFF_SSTL135_DCI
DIFF_SSTL135_T_DCI
DIFF_SSTL12_DCI
DIFF_SSTL12_T_DCI
UG471 (v1.10) May 8, 2018