Xilinx SelectIO 7 Series User Manual page 93

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One way to accomplish the above criteria is to use an external circuit that both AC-couples
and DC-biases the input signals.
AC-coupled and DC-biased circuit for a differential clock input. R
differential receiver termination because the internal DIFF_TERM is set to FALSE. To
maximize the input noise margin, all R
creating a V
typical values for the AC coupling capacitors C
components should be placed physically close to the FPGA inputs.
X-Ref Target - Figure 1-72
7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
The differential signals at the input pins meet the V
corresponding LVDS or LVDS_25 DC specifications tables of the specific device family
data sheet.
For HR I/O banks in bidirectional configuration, internal differential termination is
always used.
level of V
ICM CCO
FPGA
LVDS or
LVDS_25
Input
Buffer
Figure 1-72: Example Circuit for AC-Coupled and DC-Biased Differential
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Supported I/O Standards and Terminations
Figure 1-72 shows an example circuit for providing an
resistors should be the same value, essentially
BIAS
/2. Resistors in the 10k–100KΩ range are recommended. The
are in the range of 100 nF. All
AC
V
CCO
R
BIAS
R
BIAS
R
DIFF
P
100Ω
N
R
BIAS
R
BIAS
Clock Input
(min) requirements in the
IDIFF
provides the 100Ω
DIFF
Differential Clock
Input to the FPGA
C
AC
Differential
Transmission Line
C
AC
UG471_c1_72_050212
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