Output Delay Resources (Odelay)-Not Available In Hr Banks; Odelaye2 Primitive - Xilinx SelectIO 7 Series User Manual

Chapter 2: SelectIO Logic Resources
Output Delay Resources (ODELAY)—Not Available in HR Banks
Every HP I/O block contains a programmable absolute delay primitive called ODELAYE2.
The ODELAY can be connected to an OLOGICE2/OSERDESE2 block. ODELAY is a 31-tap,
wraparound, delay primitive with a calibrated tap resolution. Refer to the 7 series FPGA
data sheets for delay values. It can be applied to the combinatorial output path or
registered output path. It can also be accessed directly from the FPGA logic. ODELAY
allows outgoing signals to be delayed on an individual basis. The tap delay resolution is
varied by selecting an IDELAYCTRL reference clock from the range specified in the 7 series
FPGA data sheets.

ODELAYE2 Primitive

Figure 2-25
X-Ref Target - Figure 2-25
Table 2-13
Table 2-13: ODELAYE2 Primitive Ports
Port
Direction
Name
C Input
REGRST Input
LD Input
CE Input
INC Input
CINVCTRL Input
CNTVALUEIN Input
CLKIN Input
134
Send Feedback
shows the ODELAYE2 primitive.
C
REGRST
LD
CE
INC
CINVCTRL
CNTVALUEIN[4:0]
CLKIN
ODATAIN
LDPIPEEN
Figure 2-25: ODELAYE2 Primitive
lists the available ports in the ODELAYE2 primitive.
Width
1 Clock input used in VARIABLE, VAR_LOAD, or VAR_LOAD_PIPE mode.
1 Reset to all zeroes for the pipeline register.
Loads the ODELAY
1 mode. In VAR_LOAD mode, it loads the value of CNTVALUEIN. In
VAR_LOAD_PIPE mode, it loads the value currently in the pipeline register.
1 Enable increment/decrement function.
1 Increment/decrement number of tap delays.
1 Dynamically inverts the clock (C) polarity.
5 Input value from FPGA logic for dynamically loadable tap value.
1 Clock Access into the ODELAY (from the I/O CLKMUX).
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ODELAYE2
DATAOUT
CNTVALUEOUT[4:0]
Function
primitive to the pre-programmed value in VARIABLE
7 Series FPGAs SelectIO Resources User Guide
ug471_c2_23_0118
UG471 (v1.10) May 8, 2018