Hstl (High-Speed Transceiver Logic); Hstl_ I And Hstl_ I_18; Hstl_I_12; Hstl_ I_Dci And Hstl_ I_Dci_18 - Xilinx SelectIO 7 Series User Manual

Chapter 1: SelectIO Resources

HSTL (High-Speed Transceiver Logic)

The high-speed transceiver logic (HSTL) standard is a general purpose high-speed bus
standard is defined by JEDEC (JESD8-6). The HSTL standards have four variations
(classes). To support clocking high-speed memory interfaces, differential versions are also
available. 7 series FPGA I/O supports class-I for the 1.2V version of HSTL (in HP banks),
and class-I and II for the 1.5V and 1.8V versions, including the differential versions. The
differential versions of the standard require a differential amplifier input buffer and a
push-pull output buffer. The HP I/O banks also support DCI versions.

HSTL_ I and HSTL_ I_18

Table 1-19: Available I/O Bank Type
HSTL_I and HSTL_ I_18 use V
intended for use in unidirectional links.

HSTL_I_12

Table 1-20: Available I/O Bank Type
HSTL_I_12 uses V
unidirectional links.

HSTL_ I_DCI and HSTL_ I_DCI_18

Table 1-21: Available I/O Bank Type
HSTL_I_DCI and HSTL_I_DCI_18 provide on-chip split thevenin termination powered
from V
intended for use in unidirectional links.

HSTL_ II and HSTL_ II_18

Table 1-22: Available I/O Bank Type
HSTL_II and HSTL_II_18 use V
intended for use in bidirectional links.
60
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HR HP
Available Available
CCO
HR HP
N/A Available
/2 as a parallel-termination voltage (V
CCO
HR HP
N/A Available
, creating an equivalent parallel-termination voltage (V
CCO
HR HP
Available Available
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/2 as a parallel-termination voltage (V
/2 as a parallel-termination voltage (V
CCO
7 Series FPGAs SelectIO Resources User Guide
) and are
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) and is intended for use in
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) of V /2, and are
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) and are
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UG471 (v1.10) May 8, 2018