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Figure 1-50
(1.5V or 1.8V) with bidirectional termination. In a specific circuit, all drivers and receivers
must be at the same voltage level (either 1.5V or 1.8V); they are not interchangeable. Only
HP I/O banks support the DCI standards. The internal split-termination resistors are
always present, independent of whether the drivers are 3-stated.
X-Ref Target - Figure 1-50
External Termination
HSTL_II
HSTL_II_18
V
=
REF
0.75V for HSTL_II
0.9V for HSTL_II_18
DCI
V
= 1.5V for HSTL_II_DCI
CCO
HSTL_II_DCI
R
HSTL_II_DCI_18
R
V
=
REF
0.75V for HSTL_II_DCI
0.9V for HSTL_II_DCI_18
Figure 1-50: HSTL Class II (1.5V or 1.8V) Bidirectional Termination
7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
shows a sample circuit illustrating a termination technique for HSTL class-II
V
= 0.75V for HSTL_II
TT
0.9V for HSTL_II_18
IOB
R P = Z 0 = 50Ω
IOB
1.8V for HSTL_II_DCI_18
= 2Z 0 = 100Ω
VRN
= 2Z 0 = 100Ω
VRP
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Supported I/O Standards and Terminations
V
= 0.75V for HSTL_II
TT
0.9V for HSTL_II_18
IOB
R P = Z 0 = 50Ω
Z 0
IOB
V
= 1.5V for HSTL_II_DCI
CCO
1.8V for HSTL_II_DCI_18
R
= 2Z 0 = 100Ω
VRN
Z 0
V
REF
0.75V for HSTL_II_DCI
0.9V for HSTL_II_DCI_18
R
= 2Z 0 = 100Ω
VRP
HSTL_II
HSTL_II_18
+
V
=
–
REF
0.75V for HSTL_II
0.9V for HSTL_II_18
HSTL_II_DCI
HSTL_II_DCI_18
+
–
=
ug471_c1_40_121214
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