Iobuf_Intermdisable - Xilinx SelectIO 7 Series User Manual

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Chapter 1:
SelectIO Resources
Split-Termination DCI (Thevenin Equivalent Termination to VCCO/2)
3-state DCI (T_DCI)
X-Ref Target - Figure 1-25
The IOBUF_DCIEN primitive can disable the input buffer and force the O output to the
fabric to a logic High when the USE_IBUFDISABLE attribute is set to TRUE and the
IBUFDISABLE signal is asserted High. If USE_IBUFDISABLE is set to FALSE, this input is
ignored and should be tied to ground. If the I/O is using the split-termination DCI feature,
this primitive disables the termination legs whenever the DCITERMDISABLE signal is
asserted High. Only the 3-state DCI I/O standards can be used on bidirectional signals.
With 3-state DCI I/O standards, the DCI termination legs turn off whenever the driver is
active. The IOBUF_DCIEN primitive further allows the termination legs to be disabled
whenever the DCITERMDISABLE signal is asserted High. These features can be combined
to reduce power whenever the input is idle for a period of time.

IOBUF_INTERMDISABLE

The IOBUF_INTERMDISABLE primitive shown in
banks. It has an IBUFDISABLE port that can be used to disable the input buffer during
periods that the buffer is not being used. The IOBUF_INTERMDISABLE primitive also has
an INTERMDISABLE port that can be used to disable the optional uncalibrated
split-termination feature. See
(IN_TERM)
X-Ref Target - Figure 1-26
40
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for more details.
IBUFDISABLE
DCITERMDISABLE
Figure 1-25: Bidirectional Buffer With Input Path Disable and DCI Disable
for more details on this feature.
IBUFDISABLE
INTERMDISABLE
Figure 1-26: Bidirectional Buffer With Input Path Disable and IN_TERM Disable
www.xilinx.com
IOBUF_DCIEN
I
T
O
(IOBUF_DCIEN)
Figure 1-26
Uncalibrated Split Termination in High-Range I/O Banks
IOBUF_INTERMDISABLE
I
T
O
(IOBUF_INTERMDISABLE)
7 Series FPGAs SelectIO Resources User Guide
and
DCI and
I/O
UG471_c1_74_021414
is available in the HR I/O
I/O
UG471_c1_75_021414
UG471 (v1.10) May 8, 2018

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